IP Library Granted Patent US 7,376,773
Granted Patent B2
US 7,376,773 · App. 10/884,145 · Granted May 20, 2008

Multi-standard protocol storage devices and methods of operating the same

Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 7,376,773
App. No.
10/884,145
Granted
May 20, 2008
Kind
B2
Abstract

A multi-standard protocol storage device can include a non-volatile memory, a first interface controller, a second interface controller, and at least one pin. The non-volatile memory can be accessed according to a non-volatile memory protocol. The first interface controller can be configured to convert first commands in a first standardized protocol to the non-volatile memory protocol and the second interface controller can be configured to convert second commands in a second standardized protocol to the non-volatile memory protocol. The at least one pin of the device is configured to conduct a recognition signal thereon indicating whether the first or second standardized protocol is used by a host coupled thereto and that conducts data signals according to the first and second standardized protocols.

Claims (22)

1. A multi-standard protocol storage device comprising:

a non-volatile memory accessed according to a non-volatile memory protocol;

a first interface controller configured to convert first commands in a first standardized protocol to the non-volatile memory protocol;

a second interface controller configured to convert second commands in a second standardized protocol to the non-volatile memory protocol;

at least one pin configured to conduct a recognition signal thereon indicating whether the first or second standardized protocol is used by a host coupled thereto and that conducts data signals according to the first and second standardized protocols;

a plurality of pins configured to conduct a plurality of signals thereon; and

an interface recognition unit coupled to the plurality of pins and configured to determine whether a host protocol used by the host coupled to the plurality of pins comprises a standardized SmartCard protocol or one of a standardized MultiMedia Card (MMC) protocol, a standardized CompactFlash protocol, a standardized SecureDigital (SD) protocol, and a standardized MemoryStick protocol, wherein the interface recognition unit comprises:

a first level sensing circuit coupled to the at least one pin and configured to pull-up the recognition signal on the at least one pin through a pull-up load responsive to a first enable signal to provide a first voltage level for the recognition signal; and

a second level sensing circuit coupled to the at least one pin and configured to pull-down the recognition signal on the at least one pin through a pull-down load responsive to a second enable signal to provide a second voltage level for the recognition signal;

wherein the interface recognition unit is further configured to determine a type of the host based on the first and second voltage levels and enables the first or second interface controller based on the determined type of host.

2. A multi-standard protocol storage device according to claim 1 wherein the interface recognition unit is configured to determine that the type comprises a first type of host if the first and second voltage levels are logical high, the type comprises a second type of host if the first and second voltage levels are logical low, the type comprises a third type of host if the first voltage level is logical high and the second voltage level is logical low, and the type comprises a fourth type of host if the first voltage level is logical low and the second voltage level is logical high.

3. A multi-standard protocol storage device according to claim 1 wherein the non-volatile memory and the first and second interface controllers are included in a single housing.

4. A multi-standard protocol storage device comprising:

a non-volatile memory accessed according to a non-volatile memory protocol;

a first interface controller configured to convert first commands in a first standardized protocol to the non-volatile memory protocol;

a second interface controller configured to convert second commands in a second standardized protocol to the non-volatile memory protocol;

at least one pin configured to conduct a recognition signal thereon indicating whether the first or second standardized protocol is used by a host coupled thereto and that conducts data signals according to the first and second standardized protocols, wherein the first standardized protocol comprises a Universal Serial Bus (USB) standardized protocol and the second standardized protocol comprises an MMC standardized protocol;

a plurality of pins configured to conduct a plurality of signals thereon;

a first level sensing circuit coupled to the at least one pin and configured to pull-up a signal on the at least one pin through a first pull-up load responsive to a first state of an enable signal to provide a first voltage level for the signal pulled-up; and

a second level sensing circuit coupled to the at least one pin and configured to pull-up the signal through a second pull-up load, that is less than the first pull-up load, responsive to a second state of the enable signal to provide a second voltage level for the signal, wherein the first pull-up load is greater than a pull-down load included in a host coupled to the first pull-up load via the one of the plurality of pins.

5. A multi-standard protocol storage device according to claim 4 wherein the second pull-up load is less than the pull-down load.

6. A multi-standard protocol storage device according to claim 5 wherein the second level sensing circuit is enabled responsive to the multi-standard protocol storage device being coupled to an USB standardized host.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2004
From: KIM, YONG-HYEON; JEON, TAE-KEUN; KIM, SEONG-HYUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 015106/0809 →
Priority Claims (2)
KR 10-2003-0045412 · Jul 4, 2003 · national
KR 10-2003-0076729 · Oct 31, 2003 · national
Continuity (1)
Related Publication 20050005045A1 · Jan 6, 2005