Protocol converter to access AHB slave devices using the MDIO protocol

1. A method for communicating between a first bus and a second bus, comprising the steps of:

(A) recognizing a read operation code in a read frame (i) received from said first bus and (ii) communicated with a first-bus protocol;

(B) initiating a read transaction on said second bus using a second-bus protocol different than said first-bus protocol, wherein said initiating occurs earlier than a turn around time in said first-bus protocol that provides a plurality of bit times to respond to said read operation code;

(C) transmitting read data received from said second bus on said first bus immediately after said turn around time; and

(D) truncating a bit width of an address received from said first bus.

2. The method according to claim 1 , further comprising the step of:

converting said read data received from said second bus in a parallel format to a serial format prior to transmission on said first bus.

3. The method according to claim 1 , wherein said first bus is compliant with an Institute of Electrical and Electronics Engineering 802.3 standard and said second bus is compliant with an Advanced Microcontroller Bus Architecture specification.

4. The method according to claim 1 , further comprising the step of:

decoding a register address in said read frame earlier than said turn around time.

5. The method according to claim 4 , further comprising the step of:

decoding a physical address in said read frame later than said register address and earlier than said turn around time.

6. The method according to claim 5 , further comprising the step of:

continuing said read transaction in response to said

physical address and said register address respectively matching an assigned physical address and an assigned register address.

7. The method according to claim 1 , further comprising the step of:

buffering an address received from said first bus in an address frame.

8. The method according to claim 7 , wherein step (C) comprises the sub-steps of:

transmitting a first portion of said read data on said first bus in response to a particular bit of said address having a first state; and

transmitting a second portion of said read data on said first bus in response to said particular bit of said address having a second state different than said first state.

9. The method according to claim 1 , further comprising the step of:

buffering a first portion of a write data received from said first bus, without transferring said first portion to said second bus, in response to a particular bit of an address corresponding to said first portion of said write data having a first state.

10. The method according to claim 9 , further comprising the step of:

transferring both said first portion of said write data and a second portion of said write data on said second bus in response to said particular bit of said address having a second state opposite said first state.

11. A circuit comprising:

a first module configured to (i) recognize a read operation code in a frame (a) received from a first bus and (b) communicated with a first-bus protocol, (ii) transmit read data received from a second bus on said first bus immediately after a turn around time in said first-bus protocol that provides a plurality of bit times to respond to said read operation code and (iii) buffer a first portion of a write data received from said first bus, without transferring said first portion to said second bus, in response to a particular bit of an address corresponding to said first portion having a first state; and

a second module connected to said first module and configured to (i) initiate a read transaction on said second bus using a second-bus protocol different than said first-bus protocol, wherein said initiating occurs earlier than said turn around time in said first-bus protocol.

12. The circuit according to claim 11 , wherein said first bus is compliant with an Institute of Electrical and Electronics Engineering 802.3 standard and said second bus is compliant with an Advanced Microcontroller Bus Architecture specification.

13. The circuit according to claim 11 , wherein said first module comprises a first finite state machine configured to decode said frame.

14. The circuit according to claim 13 , wherein said second module comprises a second finite state machine configured to communicate with a slave device on said second bus.

15. The circuit according to claim 14 , wherein said first finite state machine is further configured to generate a request signal informing said second finite state machine to initiate said read transaction on said second bus.

16. The circuit according to claim 11 , wherein said second module is further configured to expand a bit width of an address as received from said first module prior to use of said address on said second bus.

17. The circuit according to claim 11 , wherein said first module further comprises a multiplex module configured to transfer a plurality of read portions of said read data from said second module one of said read portions at a time.

18. The circuit according to claim 17 , wherein said multiplex module is further configured to transfer a plurality of write portions of a write data to said second module one of said write portions at a time.

19. A circuit comprising:

means for recognizing a read operation code in a read frame (i) received from a first bus and (ii) communicated with a first-bus protocol;

means for initiating a read transaction to a device on a second bus using a second-bus protocol different than said first-bus protocol, wherein said initiating occurs earlier than a turn around time in said first-bus protocol that provides a plurality of bit times to respond to said read operation code;

means for transmitting read data received from said second bus on said first bus immediately after said turn around time; and

means for buffering a first portion of a write data received from said first bus, without transferring said first portion to said second bus, in response to a particular bit of an address corresponding to said first portion having a first state.

20. The circuit according to claim 19 , further comprising means for truncating a bit width of said address as received from said first bus.

21. A method for communicating between a first bus and a second bus, comprising the steps of:

(A) recognizing a read operation code in a read frame (i) received from said first bus and (ii) communicated with a first-bus protocol;

(B) initiating a read transaction on said second bus using a second-bus protocol different than said first-bus protocol, wherein said initiating occurs earlier than a turn around time in said first-bus protocol that provides a plurality of bit times to respond to said read operation code;

(C) transmitting read data received from said second bus on said first bus immediately after said turn around time;

(D) buffering an address received from said first bus in an address frame; and

(E) buffering a first portion of a write data received from said first bus, without transferring said first portion to said second bus, in response to a particular bit of said address having a first state.

22. A circuit comprising:

a first module configured to (i) recognize a read operation code in a frame (a) received from a first bus and (b) communicated with a first-bus protocol, (ii) transmit read data received from a second bus on said first bus immediately after a turn around time in said first-bus protocol that provides a plurality of bit times to respond to said read operation code and (iii) truncate a bit width of an address received from said first bus; and

a second module connected to said first module and configured to (i) initiate a read transaction on said second bus using a second-bus protocol different than said first-bus protocol, wherein said initiating occurs earlier than said turn around time in said first-bus protocol.