System for enabling and disabling voltage regulator controller of electronic appliance according to a series of delay times assigned to voltage regulator controllers
In some embodiments, a method, apparatus and system for enabling and disabling voltage regulator controllers are generally presented. In this regard, a sequencer agent is introduced to selectively enable or disable the outputs of voltage regulator controllers in an electronic appliance based at least in part on settings stored in non-volatile memory. Other embodiments are discussed and claimed.
1. An electronic appliance, comprising:
a power supply;
an electronic circuit board coupled with the power supply; and
a sequencer engine coupled with the electronic circuit board, the sequencer engine to sequentially enable voltage regulator controllers on the electronic circuit board during a power up based at least in part on settings stored in non-volatile memory, the sequencer engine to retrieve delay times for a future power state change, and the sequencer engine to prevent the power supply from changing states until voltage regulator controller outputs are stable.
2. The electronic appliance of claim 1 , further comprising:
the sequencer engine to sequentially disable voltage regulator controllers on the electronic circuit board during a power down based at least in part on settings stored in non-volatile memory.
3. An apparatus, comprising:
a non-volatile memory interface;
a power supply interface;
a voltage regulator controller interface; and
control logic coupled with the non-volatile memory, power supply and voltage regulator controller interfaces, the control logic to retrieve delay times from non-volatile memory, to enable voltage regulator controller outputs at expiration of associated delay times in response to a power up request, and to prevent a power supply from changing states until the voltage regulator controller outputs are stable.
4. The apparatus of claim 3 , further comprising control logic to disable voltage regulator controller outputs at expiration of associated delay times in response to a power down request.
5. The apparatus of claim 3 , further comprising control logic to retrieve ramp rate settings from non-volatile memory and to set voltage regulator controller output ramp rates.
6. The apparatus of claim 3 , further comprising control logic to retrieve delay times for a future power state change.