Stacked packages with interconnecting pins

1. An apparatus comprising:

a first integrated circuit package comprising a first integrated circuit die and a first integrated circuit package substrate, the first integrated circuit package substrate defining a first plurality of openings;

a second integrated circuit package comprising a second integrated circuit die and a second integrated circuit package substrate, the second integrated circuit package substrate defining a second plurality of openings; and

a third substrate comprising a plurality of conductive projections,

wherein each of the plurality of conductive projections is disposed within a respective one of the first plurality of openings and a respective one of the second plurality of openings;

wherein one of the plurality of conductive projections contacts a first conductive element of the first integrated circuit package and a second conductive element of the second integrated circuit package;

wherein the first conductive element is electrically connected to the first integrated circuit die and the second conductive element is electrically connected to the second integrated circuit die;

wherein the third substrate comprises a plurality of solder balls, and

wherein the one of the plurality of conductive projections is electrically connected to one of the plurality of solder balls.

2. An apparatus comprising:

a first integrated circuit package comprising a first integrated circuit die and a first integrated circuit package substrate, the first integrated circuit package substrate defining a first plurality of openings;

a second integrated circuit package comprising a second integrated circuit die and a second integrated circuit package substrate, the second integrated circuit package substrate defining a second plurality of openings; and

a third substrate comprising a plurality of conductive projections,

wherein each of the plurality of conductive projections is disposed within a respective one of the first plurality of openings and a respective one of the second plurality of openings;

wherein the first integrated circuit package comprises a third integrated circuit die, and

wherein the first integrated circuit die comprises a microprocessor and the third integrated circuit die comprises static random access memory.

3. An apparatus according to claim 2 ,

wherein the second integrated circuit package comprises a fourth integrated circuit die, and

wherein the second integrated circuit die comprises flash memory and the fourth integrated circuit die comprises flash memory.

4. An apparatus comprising:

a first integrated circuit package comprising a first integrated circuit die and a first integrated circuit package substrate, the first integrated circuit package substrate defining a first plurality of openings;

a second integrated circuit package comprising a second integrated circuit die and a second integrated circuit package substrate, the second integrated circuit package substrate defining a second plurality of openings; and

a third substrate comprising a plurality of conductive projections,

wherein each of the plurality of conductive projections is disposed within a respective one of the first plurality of openings and a respective one of the second plurality of openings;

wherein the first integrated circuit package comprises a first plurality of wirebonds to connect the first integrated circuit die to the first integrated circuit package substrate,

wherein the second integrated circuit package comprises a second plurality of wirebonds to connect the second integrated circuit die to the second integrated circuit package substrate.

5. An apparatus according to claim 4 , further comprising:

first mold compound disposed over the first integrated circuit die and the first plurality of wirebonds; and

second mold compound disposed over the second integrated circuit die and the second plurality of wirebonds.

6. An apparatus according to claim 5 ,

wherein the first mold compound defines a third plurality of openings,

wherein the second mold compound defines a fourth plurality of openings, and

wherein each of the plurality of conductive projections is disposed within a respective one of the third plurality of openings and a respective one of the fourth plurality of openings.

7. An apparatus comprising:

a first integrated circuit package comprising a first integrated circuit die and a first integrated circuit package substrate, the first integrated circuit package substrate defining a first plurality of openings;

a second integrated circuit package comprising a second integrated circuit die and a second integrated circuit package substrate, the second integrated circuit package substrate defining a second plurality of openings; and

a third substrate comprising a plurality of conductive projections,

wherein each of the plurality of conductive projections is disposed within a respective one of the first plurality of openings and a respective one of the second plurality of openings;

wherein the plurality of conductive projections are disposed on a first face of the third substrate,

wherein the third substrate comprises a plurality of solder balls disposed on a second face of the third substrate, and

wherein at least one of the plurality of conductive projections is electrically connected to one of the plurality of solder balls.

8. A method comprising:

fabricating a first integrated circuit package substrate defining a first plurality of openings;

coupling a first integrated circuit die to the first integrated circuit package substrate;

fabricating a second integrated circuit package substrate defining a second plurality of openings;

coupling a second integrated circuit die to the second integrated circuit package substrate; and

coupling the first integrated circuit package substrate and the second integrated circuit package substrate to a third substrate comprising a plurality of conductive projections,

wherein each of the plurality of conductive projections is coupled to a respective one of the first plurality of openings and to a respective one of the second plurality of openings;

wherein one of the plurality of conductive projections contacts a first conductive element of the first integrated circuit package and a second conductive element of the second integrated circuit package;

wherein the first conductive element is electrically connected to the first integrated circuit die and the second conductive element is electrically connected to the second integrated circuit die;

wherein the third substrate comprises a plurality of solder balls, and

wherein the one of the plurality of conductive projections is electrically connected to one of the plurality of solder balls.

9. A method comprising:

fabricating a first integrated circuit package substrate defining a first plurality of openings;

coupling a first integrated circuit die to the first integrated circuit package substrate;

fabricating a second integrated circuit package substrate defining a second plurality of openings;

coupling a second integrated circuit die to the second integrated circuit package substrate;

coupling the first integrated circuit package substrate and the second integrated circuit package substrate to a third substrate comprising a plurality of conductive projections, and

coupling a third integrated circuit die to the first integrated circuit die,

wherein each of the plurality of conductive projections is coupled to a respective one of the first plurality of openings and to a respective one of the second plurality of openings; and

wherein the first integrated circuit die comprises a microprocessor and the third integrated circuit die comprises static random access memory.

10. A method according to claim 9 , further comprising:

coupling a fourth integrated circuit die to the second integrated circuit die,

wherein the second integrated circuit die comprises flash memory and the fourth integrated circuit die comprises flash memory.

11. A method comprising:

fabricating a first integrated circuit package substrate defining a first plurality of openings;

coupling a first integrated circuit die to the first integrated circuit package substrate;

fabricating a second integrated circuit package substrate defining a second plurality of openings;

coupling a second integrated circuit die to the second integrated circuit package substrate;

coupling the first integrated circuit package substrate and the second integrated circuit package substrate to a third substrate comprising a plurality of conductive projections,

connecting a first plurality of wirebonds to the first integrated circuit die and to the first integrated circuit package substrate; and

connecting a second plurality of wirebonds to the second integrated circuit die and to the second integrated circuit package substrate;

wherein each of the plurality of conductive projections is coupled to a respective one of the first plurality of openings and to a respective one of the second plurality of openings.

12. A method according to claim 11 , further comprising:

depositing first mold compound over the first integrated circuit die and the first plurality of wirebonds; and

depositing second mold compound disposed over the second integrated circuit die and the second plurality of wirebonds.

13. A method according to claim 12 ,

wherein the first mold compound defines a third plurality of openings,

wherein the second mold compound defines a fourth plurality of openings, and

wherein each of the plurality of conductive projections is disposed within a respective one of the third plurality of openings and a respective one of the fourth plurality of openings.

14. A method comprising:

fabricating a first integrated circuit package substrate defining a first plurality of openings;

coupling a first integrated circuit die to the first integrated circuit package substrate;

fabricating a second integrated circuit package substrate defining a second plurality of openings;

coupling a second integrated circuit die to the second integrated circuit package substrate; and

coupling the first integrated circuit package substrate and the second integrated circuit package substrate to a third substrate comprising a plurality of conductive projections,

wherein each of the plurality of conductive projections is coupled to a respective one of the first plurality of openings and to a respective one of the second plurality of openings;

wherein the plurality of conductive projections are disposed on a first face of the third substrate,

wherein the third substrate comprises a plurality of solder balls disposed on a second face of the third substrate, and

wherein at least one of the plurality of conductive projections is electrically connected to one of the plurality of solder balls.

15. A system comprising:

a microprocessor die;

a first integrated circuit package substrate coupled to the microprocessor die, the first integrated circuit package substrate defining a first plurality of openings;

a memory die;

a second integrated circuit package substrate coupled to the memory die, the second integrated circuit package substrate defining a second plurality of openings;

a third substrate comprising a plurality of conductive projections, each of the plurality of conductive projections being disposed within a respective one of the first plurality of openings and a respective one of the second plurality of openings;

a motherboard connected to the third substrate; and

a graphics controller connected to the motherboard.

16. A system according to claim 15 ,

wherein one of the plurality of conductive projections contacts a first conductive element of the first integrated circuit package and a second conductive element of the second integrated circuit package.

17. A system according to claim 16 ,

wherein the first conductive element is electrically connected to the microprocessor die and the second conductive element is electrically connected to the memory die.

18. A system according to claim 15 , further comprising:

a second memory die coupled to the microprocessor.

19. A system according to claim 15 , further comprising:

a first plurality of wirebonds connecting the microprocessor die to the first integrated circuit package substrate;

a second plurality of wirebonds connecting the memory die to the second integrated circuit package substrate;

first mold compound disposed over the microprocessor die and the first plurality of wirebonds; and

second mold compound disposed over the memory die and the second plurality of wirebonds.

20. A system according to claim 19 ,

wherein the first mold compound defines a third plurality of openings,

wherein the second mold compound defines a fourth plurality of openings, and wherein each of the plurality of conductive projections is disposed within a respective one of the third plurality of openings and a respective one of the fourth plurality of openings.