Shift register

1. A shift register having a plurality of stages for shifting an input signal using first and second driving voltages, first and second clock signals and a start pulse, each of said plurality of stages comprising:

an output buffer for selectively applying any one of the first and second clock signals and the second driving voltage to an output line under control of first and second nodes;

a pre-charger for pre-charging the first driving voltage into the first node in response to said start pulse;

a second node controller for selectively supplying the first and second driving voltages to the second node in such a manner to be opposite to the first node using said start pulse and an output signal of the next stage; and

a first node controller for supplying the second driving voltage to the first node in a time interval excluding the time interval for said pre-charging.

2. The shift register according to claim 1 , wherein said second clock signal has a phase opposite to said first clock signal.

3. The shift register according to claim 1 , wherein said first and second clock signals are alternately applied to the plurality of stages.

4. The shift register according to claim 1 , wherein said first driving voltage is higher than said second driving voltage.

5. The shift register according to claim 1 , wherein the pre-charger includes:

a first transistor connected between an input line of said first driving voltage and the first node to be controlled by said start pulse.

6. The shift register according to claim 5 , wherein the second node controller includes:

a second transistor connected to an input line of said first driving voltage and a third node in a diode type;

a third transistor connected, in parallel, to the second transistor to be controlled by an output signal of the next stage;

a fourth transistor connected between a third node and an input line of said second driving voltage to be controlled by said start pulse;

a fifth transistor connected, in parallel, to the fourth transistor to be controlled by the first node;

a sixth transistor connected between the input line of said first driving voltage and the second node to be controlled by the third node; and

a seventh transistor connected between the second node and the input line of said second driving voltage to be controlled by the first node.

7. The shift register according to claim 6 , wherein the second and third nodes are always supplied with said first driving voltage in a time interval when the output buffer supplies said second driving voltage.

8. The shift register according to claim 6 , wherein the first node controller includes:

an eighth transistor connected between the first node and the input line of said second driving voltage to be controlled by the second node.

9. The shift register according to claim 8 , wherein the output buffer includes:

a ninth transistor connected between the input line of any one of said clock signals and the output line to be controlled by the first node; and

a tenth transistor connected between the output line and the input line of said second driving voltage to be controlled by the second node.

10. The shift register according to claim 9 , wherein the output buffer includes:

a capacitor connected to the ninth transistor to boot-strap the pre-charged first node using any one of said clock signals.

11. The shift register according to claim 9 , wherein the first node controller includes:

an eleventh transistor connected, in parallel, to the eighth transistor to be controlled by an output signal of the next stage.

12. The shift register according to claim 1 , wherein one of the stages is configured by the same channel-type transistor.

13. The shift register according to claim 1 , wherein one of the stages is configured by NPMOS transistors.

14. The shift register according to claim 1 , wherein one of the stages is configured by an amorphous-silicon thin film transistor.

15. The shift register according to claim 1 , wherein said start pulse is a signal from the external thereof or an output signal of the previous stage.

16. A display device having a shift register, wherein the shift register includes at least two stages for shifting an input signal and receives first and second driving voltages, first and second clock signals and a start pulse, each of the two stages comprising:

an output buffer for selectively applying any one of the first and second clock signals and the second driving voltage to an output line under control of first and second nodes;

a pre-charger for pre-charging the first driving voltage into the first node in response to the start pulse;

a second node controller for selectively supplying the first and second driving voltages to the second node in such a manner to be opposite to the first node using the start pulse and an output signal of the next stage; and

a first node controller for supplying the second driving voltage to the first node in a time interval excluding the time interval for the pre-charging.

17. The display device according to claim 16 , wherein the start pulse is a signal from the external thereof or an output signal of the previous stage.

18. The display device according to claim 16 , wherein the two stages of the shift register is configured with an amorphous silicon thin film transistor.

19. The display device according to claim 16 , wherein the display device is a liquid crystal display device or an electroluminescence diode.

20. The display device according to claim 16 , wherein the pre-charger further includes a transistor connected between an input line of the first driving voltage and the first node to be controlled by the start pulse.