Thin film transistor with a passivation layer
View Patent ↗Apparatus comprising a thin film transistor having passivation layer disposed adjacent to a second surface of said channel layer, wherein said passivation layer comprises one or more wide-bandgap dielectric materials.
1. An apparatus, comprising:
at least one thin film transistor (TFT) having:
a substrate;
a channel layer disposed over at least a portion of the substrate, wherein said channel layer comprises a semiconductive oxide, and wherein said channel layer comprises at least a first surface and a substantially opposing second surface;
a gate dielectric layer disposed adjacent to said first surface of said channel layer;
a passivation layer disposed adjacent to said second surface of said channel layer, wherein said passivation layer comprises one or more wide-bandgap dielectric materials.
2. The apparatus of claim 1 , and further comprising:
one or more gate electrodes formed over at least a portion of said substrate, wherein the gate electrode is electrically coupled to said gate dielectric layer; and
one or more drain and source electrodes formed over at least a portion of said substrate, wherein said drain and source electrodes are electrically coupled to said channel layer.
3. The apparatus of claim 2 , wherein said TFT comprises a bottom gate TFT.
4. The apparatus of claim 1 , wherein said at least one TFT comprises a plurality of thin film transistors, wherein at least a portion of said thin film transistors are coupled to form circuitry.
5. The apparatus of claim 4 , wherein said circuitry substantially comprises at least a portion of a display device.
6. The apparatus of claim 5 , wherein said at least a portion of a display device comprises a backplane of an Active Matrix Liquid Crystal Display (AMLCD) device.
7. The apparatus of claim 4 , wherein said circuitry substantially comprises at least a portion of a smart package.
8. The apparatus of claim 1 , wherein said channel layer comprises one or more of: zinc oxide, cadmium oxide, indium oxide, gallium oxide, tin oxide, silver oxide, copper oxide, germanium oxide, lead oxide and/or antimony oxide.
9. The apparatus of claim 1 , wherein said channel layer is substantially comprised of an oxide comprising two or more of: zinc, cadmium, indium, gallium, tin, silver, copper, germanium, lead and/or antimony.
10. The apparatus of claim 1 , wherein said gate dielectric layer comprises one or more of: zirconium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, silicon oxide, aluminum oxide, hafnium oxide, barium zirconate titanate, barium strontium titanate, silicon nitride, and/or silicon oxynitride.
11. The apparatus of claim 1 , wherein said passivation layer comprises one or more of: SiO x , SiN x , SiO x N y , SiO x C y , SiO x C y H z , SiO x F y , GeO x , AlO x , GaO x , SbO x , ZrO x , HfO x , TaO x , YO x , VO x , MgO x , MgF x , CaO x , CaF x , BaO x , BaF x , SrO x , SrF x , and/or one or more types of spin-on glass.
12. The apparatus of claim 1 , wherein said passivation layer substantially comprises at least a portion of an interlevel dielectric layer.
13. The apparatus of claim 1 , wherein said substrate comprises one or more of: glass, silicon, silicon dioxide, and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polycarbonates (PC), polyethylenenaphthalates (PEN), and/or acrylics.
14. An apparatus, comprising:
means for forming a thin film transistor (TFT) having;
a substrate;
a channel layer disposed over at least a portion of the substrate, wherein said channel layer comprises a semiconductive oxide, and wherein said channel layer comprises at least a first surface and a substantially opposing second surface;
a gate dielectric layer disposed adjacent to said first surface of said channel layer;
means for passivating, wherein said means for passivating comprises a passivation layer disposed adjacent to said second surface of said channel layer, wherein said passivation layer comprises one or more wide-bandgap dielectric materials.
15. The apparatus of claim 14 , and further comprising:
means for forming one or more gate electrodes over at least a portion of said substrate, wherein the gate electrode is electrically coupled to said gate dielectric layer; and
means for forming one or more drain and source electrodes over at least a portion of said substrate, wherein said drain and source electrodes are electrically coupled to said channel layer.
16. The apparatus of claim 15 , wherein said TFT comprises a bottom gate TFT.
17. The apparatus of claim 15 , wherein said apparatus comprises a plurality of thin film transistors, wherein at least a portion of said thin film transistors are coupled to form circuitry.
18. The apparatus of claim 15 , wherein said circuitry substantially comprises at least a portion of a display device.
19. The apparatus of claim 18 , wherein said at least a portion of a display device comprises a backplane of an Active Matrix Liquid Crystal Display (AMLCD) device.
20. The apparatus of claim 15 , wherein said at least one circuit substantially comprises at least a portion of a smart package.
21. The apparatus of claim 15 , wherein said channel layer substantially comprises one or more of: zinc oxide, cadmium oxide, indium oxide, gallium oxide, tin oxide, silver oxide, copper oxide, germanium oxide, lead oxide and/or antimony oxide.
22. The apparatus of claim 15 , wherein said channel layer substantially comprises an oxide comprising two or more of: zinc, cadmium, indium, gallium, tin, silver, copper, germanium, lead and/or antimony.
23. The apparatus of claim 15 , wherein said gate dielectric layer substantially comprises one or more of: zirconium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, silicon oxide, aluminum oxide, hafnium oxide, barium zirconate titanate, barium strontium titanate, silicon nitride, and/or silicon oxynitride.
24. The apparatus of claim 15 , wherein said means for passivating substantially comprises a layer of one or more of: SiO x , SiN x , SiO x N y , SiO x C y , SiO x C y H z , SiO x F y , GeO x , AlO x , GaO x , SbO x , ZrO x , HfO x , TaO x , YO x , VO x , MgO x , MgF x , CaO x , CaF x , BaO x , BaF x , SrO x , SrF x , and/or one or more types of spin-on glass.
25. The apparatus of claim 15 , wherein said means for passivating substantially comprises at least a portion of an interlevel dielectric layer.
26. The apparatus of claim 15 , wherein said gate dielectric layer is formed on at least a portion of a substrate, and said substrate substantially comprises one or more of: glass, silicon, silicon dioxide, and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polycarbonates (PC), polyethylenenaphthalates (PEN), and/or acrylics.