Method for fabricating semiconductor device
A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention provides a channel region formed over a device isolation structure to form a semiconductor device including a SOI (Silicon-on-Insulator) channel structure, thereby decreasing ion implanting concentration of a channel region and improving t WR (Write Recovery time) and LTRAS (Long Time for Row Address Strobe) characteristics of the device.
1. A method for fabricating a semiconductor device, the method comprising:
(a) forming a device isolation structure defining an active region on a semiconductor substrate having a pad insulating film;
(b) forming a patterned mask layer over the device isolation structure, the patterned mask layer defining an opening that exposes the device isolation structure and the pad insulating film;
(c) etching the exposed device isolation structure using the patterned mask layer to form a recess exposing sidewalls of the active region;
(d) removing the patterned mask layer;
(e) forming an epitaxial layer in the recess using the exposed sidewalls of the active region as a seed layer;
(f) selectively etching the epitaxial layer by a predetermined thickness to form a SOI (Silicon-on-Insulator) channel region in the recess;
(g) removing the pad insulating film to expose the active region;
(h) forming a gate insulating film over the exposed active region including the SOI channel region;
(i) forming a gate conductive layer over the gate insulating film; and
(j) patterning the gate conductive layer to form a gate structure.
2. The method according to claim 1 , wherein the active region corresponds to a bit line contact region or a storage node contact region.
3. The method according to claim 1 , wherein the opening is a region extending a bit line contact region to neighboring storage node contact regions.
4. The method according to claim 1 , wherein the pad insulating film includes a pad oxide film and a pad nitride film.
5. The method according to claim 1 , wherein the patterned hard mask layer is selected from the group consisting of a nitride film, a polysilicon film, an amorphous Carbon film, a SiON film and combinations thereof.
6. The method according to claim 1 , wherein a process for forming the epitaxial layer is performed by a solid phase epitaxy method.
7. The method according to claim 1 , wherein a process for removing the pad insulating film is performed by a wet or dry etching method.
8. The method according to claim 1 , wherein the thickness of the SOI channel region ranges from about 50 A to about 200 A.
9. The method according to claim 1 , wherein the gate conductive layer comprises an upper gate conductive layer and a lower gate conductive layer.
10. The method according to claim 1 , wherein forming a device isolation structure includes forming a liner oxide film and a liner nitride film over the semiconductor substrate.
11. The method according to claim 10 , wherein a process for removing the liner nitride film is performed by a wet or dry etching method.
12. The method according to claim 10 , wherein a process for removing the liner oxide film is performed by an anisotropic etching method.