Flip chip metallization method and devices
Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wetable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in implantable electronic devices such as neural electrode arrays.
1. A method of interconnect metallization for an electronic device having electrical contacts exposed through a passivation layer, comprising the steps of:
a) depositing an adhesion layer on the electrical contacts, the adhesion layer including titanium;
b) depositing a diffusion barrier layer on the adhesion layer, the diffusion barrier layer including platinum;
c) depositing a wetable layer on the diffusion barrier layer, the wetable layer including gold; and
d) depositing a wetting stop layer on a portion of the wetable layer, the wetting stop layer including titanium and tungsten.
2. The method of claim 1 , wherein depositing the adhesion layer on the electrical contacts further comprises depositing the adhesion layer on a portion of the passivation layer.
3. The method of claim 1 , further comprising the step of using photolithography to define features within at least one of the adhesion layer, diffusion barrier, wetable layer, and wetting stop layer.
4. The method of claim 3 , further comprising the step of performing a lift off process to define features within at least one of the adhesion layer, diffusion barrier, wetable layer, and wetting stop layer.
5. The method of claim 1 , further comprising the step of attaching solder bumps to an exposed portion of the wetable layer.
6. The method of claim 5 , wherein attaching the solder bumps is performed by any of either screening a solder paste onto the wetable layer, attaching preformed solder bumps to the wetable layer, or electroplating solder bumps onto the wetable layer.
7. The method of claim 5 , further comprising the step of soldering the electronic device to an integrated circuit to form an integrated neural probe, wherein the electronic device is an electrode array.
8. The method of claim 1 , wherein the solder balls consist essentially of a mixture of 80% gold and 20% tin.
9. The method of claim 1 , wherein the diffusion layer consists essentially of platinum.
10. The method of claim 1 , wherein the wetting stop layer consists essentially of titanium and tungsten.
11. The method of claim 1 , wherein the electronic device is an electrode array.
12. The method of claim 1 , wherein the electronic device is an integrated circuit die.
13. A product produced by the method of claim 1 .
14. A device compatible with flip chip bonding, comprising:
a) an electronic device having a plurality of electrical interconnects disposed in a planar array and exposed through a passivation layer; and
b) an underbump metallization stack disposed on at least one exposed electrical interconnect, the underbump metallization stack comprising:
i) an adhesion layer disposed on the electrical interconnect, the adhesion layer including titanium;
ii) a diffusion barrier disposed over the adhesion layer, the diffusion layer include platinum;
iii) a wetable layer disposed over the diffusion layer, the wetable layer including gold; and
iv) a wetting stop layer disposed over the wetable layer, the wetting stop layer including titanium and tungsten.
15. The device of claim 14 , wherein the passivation layer comprises silicon nitride.
16. The device of claim 14 , wherein:
the adhesion layer has a thickness of about 50 nanometers;
the diffusion barrier has a thickness of about 150 nanometers;
the wetable layer has a thickness of about 150 nanometers; and
the wetting stop layer has a thickness of about 100 nanometers.
17. The device of claim 14 , wherein:
the adhesion layer consists essentially of titanium;
the diffusion layer consists essentially of platinum;
the wetable layer consists essentially of gold; and
the wetting stop layer consists essentially of titanium and tungsten.
18. The device of claim 14 , wherein the diffusion layer consists essentially of platinum.
19. The device of claim 14 further comprising solder bumps attached to a portion of the wetable layer, the solder bumps consisting essentially of a mixture of 80% gold and 20% tin.
20. The device of claim 14 , wherein the adhesion layer, diffusion barrier, and wetable layer define a plurality of octagonal shaped areas for attachment of solder bumps thereto.