Method, microprocessor system for critical safety regulations and the use of the same
In a method of operating a microprocessor system provided with safety functions, which comprises two or more processor cores ( 1, 2 ) and periphery elements ( 5, 7 ) on a common chip carrier, to which the cores can have access for write or read operations, a distinction is made between algorithms for safety-critical functions and algorithms for comfort functions. Further, a microprocessor system appropriate for implementing the method, and the use of the same, has process cores connected to periphery elements ( 5,6,7,8,9,10 ) by way of bus systems ( 3, 4 ), and bus driver circuits ( 19 ) can transmit bus information from one bus to another with the provision of at least one address comparator ( 18 ).
1. A method of operating a microprocessor system provided with safety functions, which comprises two or more processor cores ( 1 , 2 ) on a joint chip carrier, the microprocessor system comprising periphery elements ( 5 , 7 ) to which the cores can have access for write or read operations,
including the steps of
making a distinction between algorithms for safety-critical functions and algorithms for comfort functions,
storing safety-critical data in critical-data ranges,
storing comfort-related data in uncritical-data ranges ( 12 ),
generating, by means of the safety-critical functions, input/output operations for a first type of devices intended for safety functions, and
generating, by means of the comfort functions, input/output operations for a second type of devices intended for comfort functions
wherein exclusively critical algorithms are stored in two or more first separate chip ranges or components ( 20 ) of two or more read-only memories ( 5 and 8 ) or corresponding partial ranges of respectively contiguous joint read-only memories ( 5 , 7 and 8 , 9 ), and exclusively comfort algorithms are stored in two or more other separate chip ranges or components ( 21 ) of the read-only memory ( 7 and 9 ) or in corresponding other partial ranges of respectively contiguous joint read-only memories ( 5 , 7 and 8 , 9 ).
2. The method as claimed in claim 1 , wherein access to address ranges of the periphery elements allocated to the safety algorithms is possible only when a safety algorithm controls the system program run, and access to ranges of the periphery elements allocated to the comfort algorithms are allowed only when comfort algorithms control the system program run.
3. The method as claimed in claim 1 , wherein the periphery elements comprise read-only memories ( 5 , 7 , 8 , 9 ) in which algorithms for functions that mainly serve comfort, are stored in addition to algorithms for safety-critical functions.
4. The method as claimed in claim 1 , wherein upon occurrence of an erroneous write access of a comfort algorithm, an erroneous memory access is identified and the incorrect data value corrected.
5. The method as claimed in claim 1 , wherein a comparison of data lying on data buses ( 3 , 4 ) is not made in a read operation in at least one predetermined address range.
6. A microprocessor system for at least partly safety-critical regulations, comprising at least two processor cores ( 1 , 2 ) which are connected to periphery elements ( 5 , 6 , 7 , 8 , 9 , 10 ) by way of at least two bus systems ( 3 , 4 ) associated with the cores, and at least two bus driver circuits ( 19 ) able to transmit bus information from one bus to the other bus,
wherein the microprocessor comprises at least one address comparator ( 18 ) comparing the addresses of at least one processor core with at least one established address range, and
wherein a bridging device ( 19 ) is provided that can be actuated by the address comparator ( 18 ) by way of a connection ( 13 ), said bridging device deactivating or bridging one or more data comparators ( 16 , 17 ) in dependence on the result of the comparison of addresses.
7. The microprocessor system as claimed in claim 6 , wherein the microprocessor comprises at least one data comparator ( 16 , 17 ) which detects a writing error in the periphery elements by comparing data of the first bus with data of another bus.
8. The microprocessor system as claimed in claim 6 , wherein the bus systems have substantially the same design.
9. The microprocessor system as claimed in claim 6 , wherein the periphery elements comprise at least read-write memories ( 10 ), read-only memories ( 5 , 7 , 8 , 9 ) and input/output elements ( 10 ).
10. The microprocessor system as claimed in claim 6 , wherein the comparator of addresses comprises logical components, in particular binary comparators.
11. The microprocessor system as claimed in claim 6 , wherein at least one element of the group consisting of address comparator ( 18 ), comparator ( 16 , 17 ) and driver ( 19 ) is designed redundantly.