Packaged system of semiconductor chips having a semiconductor interposer

1. A method for fabricating a semiconductor system, comprising the steps of:

forming a semiconductor interposer by the steps of:

providing a semiconductor wafer having a thickness and a first and a second surface;

fabricating conductive lines, discrete components, and circuits on the first surface;

forming via holes having sidewalls to extend from the first surface downward to a depth;

forming an insulating layer over the first and the second surface including the via hole sidewalls;

removing semiconductor material from the second wafer surface until the via holes are exposed;

depositing copper to fill the holes and form terminals on the first and second surfaces;

depositing non-reflow metal studs on the terminals; and

singulating the wafer into individual interposers having a dimension, and selecting a first individual interposer;

providing a first semiconductor chip having a dimension narrower than the interposer dimension, an active surface, and terminals with non-reflow metal studs on the active surface;

flip-attaching the first chip to the first surface of the first selected interposer so that the interposer dimension projects over the chip dimension;

providing an insulating substrate having a third and a fourth surface with terminals, conductive lines between the surfaces, conductive vias extending from the third to the fourth surface, contacting the lines;

depositing reflow bodies on the terminals of the third substrate surface;

contacting the studs on the second surface of the projecting interposer with the reflow bodies on the third substrate surface; and

reflowing the bodies around the studs to attach the interposer to the substrate.

2. The method according to claim 1 further including the step of attaching reflow bodies to the terminals on the fourth substrate surface.

3. The method according to claim 1 further including the step of encapsulating the chip, the interposer, and portions of the third substrate surface in packaging material.

4. The method according to claim 1 further including the steps of:

providing a second semiconductor chip having a dimension narrower than the interposer dimension, and an active surface including terminals with non-reflow studs; and

flip-attaching the second chip to the second interposer surface so that the interposer dimension projects over the chip dimension.

5. The method according to claim 1 further including the steps of:

providing a second semiconductor chip having a dimension narrower than the interposer dimension, and an active surface including terminals with non-reflow studs; and

flip-attaching the second chip to the third substrate surface so that the interposer dimension projects over the chip dimension.

6. The method according to claim 1 further including the step of:

selecting a second individual interposer having a dimension;

providing a second semiconductor chip having a dimension narrower than the dimension of the second interposer, and an active surface including terminals with non-reflow studs;

flip-attaching the second chip to the second interposer so that the interposer dimension projects over the chip dimension;

depositing reflow bodies on the terminals of the first surface of the projecting first interposer;

contacting the non-reflow metal studs on the projecting second interposer with the reflow bodies on the terminals of the projecting first interposer surface; and

reflowing the bodies around the studs to attach the second interposer to the first interposer.