Nonvolatile memory devices having enhanced bit line and/or word line driving capability
Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.
1. An integrated circuit memory device, comprising:
a memory array have a plurality of columns of PRAM cells therein;
a local bit line electrically coupled to a first one of the plurality of columns of PRAM cells; and
first and second bit line selection circuits configured to electrically connect first and second portions of said local bit line, respectively, to a global bit line during an operation to read data from a selected one of the PRAM cells in the first one of the plurality of columns of PRAM cells.
2. The memory device of claim 1 , wherein the first and second portions of said local bit line are first and second ends of said local bit line, respectively.
3. The memory device of claim 2 , wherein said first and second bit line selection circuits are further configured to electrically connect the first and second ends of said local bit line to the global bit line during an operation to write data to the selected one of the PRAM cells.
4. The memory device of claim 3 , wherein said first and second bit line selection circuits are responsive to equivalent column selection signals.
5. The memory device of claim 1 , wherein the PRAM cells are selected from a group consisting of diode-controlled PRAM cells and transistor-controlled PRAM cells.
6. The memory device of claim 1 , wherein said memory array includes a row of PRAM cells therein and a local word line electrically coupled to the row of PRAM cells; and wherein the memory device further comprises first and second word line driver circuits electrically connected to first and second spaced-apart nodes on the local word line, respectively, said first and second word line driver circuits configured to drive the first and second spaced-apart nodes at the same voltage level during an operation to read data from a selected one of the PRAM cells in the row.
7. The memory device of claim 6 , wherein the first and second spaced-apart nodes are located at opposing ends of the local word line.