Transistor device having an increased threshold stability without drive current degradation
By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.
1. A method, comprising:
forming a recess adjacent to a channel region of a field effect transistor;
forming a doped region in said recess by an epitaxial growth process, said doped region comprising a first dopant species of a first conductivity type;
replacing a portion of said doped region by a semiconductor material; and
introducing a second dopant species of a second conductivity type other than said first conductivity type into said semiconductor material so as to form a PN junction with said first dopant species adjacent to said channel region.
2. The method of claim 1 , wherein replacing a portion of said doped region comprises forming a second recess adjacent to said channel region and forming said semiconductor material by an epitaxial growth process.
3. The method of claim 2 , wherein said second dopant species is at least partially introduced in said semiconductor material during said epitaxial growth process.
4. The method of claim 2 , wherein said second dopant species is at least partially introduced in said semiconductor material by an implantation process.
5. The method of claim 2 , wherein said semiconductor material is formed as a strained semiconductor material.
6. The method of claim 5 , wherein said semiconductor material is a compressively strained semiconductor material.
7. The method of claim 5 , wherein said semiconductor material is formed with a tensile strain.
8. The method of claim 1 , wherein said recess is formed by an etch process on the basis of an etch mask covering said channel region, and wherein said etch process is controlled to provide a defined under-etching of said etch mask.
9. A method, comprising:
forming a recess in a crystalline semiconductor region so as to extend below an etch mask formed above said crystalline semiconductor region;
forming a doped region extending below said etch mask by a selective epitaxial growth process, said doped region comprising a first dopant species of a first conductivity type;
removing a portion of said doped semiconductor region by an anisotropic etch process; and
forming a semiconductor material in said recess after removing said portion of said doped semiconductor region, said semiconductor material comprising a second dopant species of a second conductivity type other than said first conductivity type, said first and second dopant species forming a PN junction.
10. The method of claim 9 , wherein said etch mask comprises a gate electrode of a field effect transistor.
11. The method of claim 9 , wherein said semiconductor material is formed by a selective epitaxial growth process.
12. The method of claim 11 , wherein said semiconductor material is formed as a strained semiconductor material.
13. A semiconductor device, comprising:
a gate electrode structure formed above a channel region;
a drain region and a source region formed in a recess, a first portion of the recess adjacent the channel region being lined by a first doped region, and a second portion of the recess adjacent the first portion being lined and filled by a semiconductor material without being lined by the first doped region, the first doped region comprising an epitaxially-grown material including a first dopant species of a first conductivity type and being disposed adjacent said channel region, the semiconductor material comprising a second dopant species of a second conductivity type other than said first conductivity type, said first and second dopant species forming a PN junction adjacent to said channel region in said first portion, said drain and source regions having a low resistance region of reduced concentration of counter-doping in said second portion compared to a concentration of counter-doping at said PN junction; and
a metal silicide region formed in said drain and source regions, said metal silicide region connecting to said low resistance region.
14. The semiconductor device of claim 13 , wherein said drain and source regions comprise a strained semiconductor material.
15. A method, comprising:
forming a recess in a crystalline semiconductor region so as to extend below an etch mask formed above said crystalline semiconductor region;
forming within said recess under said etch mask a doped sacrificial layer including a first dopant species of a first conductivity type;
heat treating said doped sacrificial layer to drive a portion of said first dopant species into said crystalline semiconductor region to define a doped region extending below said etch mask;
removing said doped sacrificial layer; and
forming a semiconductor material in said recess, said semiconductor material comprising a second dopant species of a second conductivity type other than said first conductivity type, said first and second dopant species forming a PN junction.
16. The method of claim 15 , wherein forming said doped sacrificial layer comprises depositing said doped sacrificial layer and removing a portion of said doped sacrificial layer by an anisotropic etch process prior to heat treating said doped sacrificial layer.
17. The method of claim 15 , wherein said etch mask comprises a gate electrode of a field effect transistor.
18. The method of claim 15 , wherein said semiconductor material is formed by a selective epitaxial growth process.
19. The method of claim 18 , wherein said semiconductor material is formed as a strained semiconductor material.