Multi-bit non-volatile memory device having a dual-gate and method of manufacturing the same, and method of multi-bit cell operation

1. A multi-bit non-volatile memory device having a dual gate structure, comprising:

a silicon substrate;

a lower insulating film formed over the silicon substrate;

a silicon layer formed over the lower insulating film and, having a silicon pin at the center of the silicon layer in which a source region and a drain region are formed on both sides of the silicon pin and the silicon pin is formed to have a shape having corners;

sequentially formed tunneling oxide film, electron trap film and a control oxide film positioned relative to the center of the silicon pin;

gate material over the control oxide film; and

wherein the source and drain regions are asymmetrically formed in a silicon channel and the silicon pin is formed to have a wider region at the source region than at the drain region.

2. The memory device of claim 1 , wherein each of the tunneling oxide films on both sides of the silicon pin has different widths or dielectric constants.

3. The memory device of claim 1 , wherein the tunneling oxide film has asymmetrical thickness or dielectric constants.

4. A method of operating a memory device, comprising:

in a multi-bit non-volatile memory device having a dual gate structure,

wherein in a read operation of electrons trapped at the electron trap film, values of threshold voltages between a normal direction read (V D >V S ) condition and a reverse direction read (V D >V S ) condition are different depending on a location where the electrons are trapped,

wherein in the case where a read operation is performed on a program in which electrons are trapped at the electron trap film of drain-side silicon pin corners, the reverse direction read (V D >V S ) condition having an opposite direction to that of an operating voltage (V D >V S ) of the program is employed, and

in the case where a read operation is performed on a program in which electrons are trapped closer toward the center of the channel and away from the source-side silicon pin corners, the normal direction read (V D >V S ) condition having an opposite direction to that of an operating voltage (V D >V S ) of the program is employed.

5. The method as claimed in claim 4 , wherein in a read operation, a 2-bit operation can be implemented using both normal and reverse direction read conditions.

6. The method as claimed in claim 4 , wherein in a read operation, a 2-bit operation can be implemented employing any one of normal and reverse direction read conditions by using different threshold voltages.

7. The method as claimed in claim 6 , wherein in a read operation, a 3-bit operation can be implemented using both the normal and reverse direction read conditions.

8. The method as claimed in claim 4 , wherein in a read operation, a 4-bit operation can be implemented using both normal and reverse direction read conditions.

9. The method as claimed in claim 4 , wherein in a read operation, a 4-bit operation can be implemented employing any one of normal and reverse direction read conditions by using different threshold voltages.

10. The method as claimed in claim 9 , wherein in a read operation, a 5-bit operation can be implemented using both the normal and reverse direction read conditions.