Semiconductor device and method for manufacturing the same

1. A semiconductor device comprising:

a first metal pattern formed on a semiconductor substrate;

a first interlayer insulating layer formed on the first metal pattern;

a second metal pattern formed on the first interlayer insulating layer;

a second interlayer insulating layer formed on the second metal pattern;

a dielectric layer and conductive layer formed on sidewalls of a first trench formed in the second interlayer insulating layer, the first trench selectively exposing a significant portion of the second metal pattern, and the dielectric layer also being formed on the significant portion of the second metal pattern and on sidewall portions of a second trench formed in the first interlayer insulating layer, the second trench exposing a significant portion of the first metal pattern, and the dielectric layer also being formed on the significant portion of the first metal pattern;

wherein the second trench is formed self-aligned using the second metal pattern as a mask;.and

a third metal pattern formed on the dielectric layer and conductive layer.

2. The device of claim 1 , wherein the conductive layer is sequentially formed on the dielectric layer.

3. The device of claim 1 , wherein the conductive layer comprises tungsten or a tungsten alloy.

4. The device of claim 1 , further comprising:

a first metal interconnection formed on the substrate; and

a second metal interconnection formed in the first interlayer insulating layer.

5. The device of claim 1 , further comprising:

a third metal interconnection formed on the second interlayer insulating layer.

6. The device of claim 1 , wherein the first, second, and third metal patterns are formed from a material comprising aluminum.

7. The device of claim 2 , wherein at least portions of the first and second metal patterns collectively comprise a capacitor lower electrode.

8. The device of claim 7 , further comprising:

at least one first contact plug electrically connecting the first and second metal patterns.

9. The device of claim 8 , wherein at least one first contact plug is formed through the first interlayer insulating layer outside the first trench.

10. The device of claim 1 , wherein the dielectric layer is sequentially formed on the conductive layer.

11. The device of claim 10 , wherein at least portions of the first and second metal patterns and conductive layer collectively form a capacitor lower electrode.

12. The device of claim 4 , further comprising:

a second contact plug electrically connecting the first and second metal interconnections through the first interlayer insulating layer.

13. The device of claim 5 , further comprising:

a third contact plug electrically connecting the second and third metal interconnections through the second interlayer insulating layer.

14. The device of claim 5 , wherein the first, second, and third metal interconnections are formed from a material comprising aluminum.

15. The device of claim 13 , wherein the third contact plug is formed of the same material as the conductive layer.

16. A method for manufacturing a semiconductor device comprising:

forming a first metal pattern on a substrate;

forming a first interlayer insulating layer on the first metal pattern;

forming a second metal pattern on the first interlayer insulating layer;

forming a second interlayer insulating layer on the second metal pattern;

forming a first trench in the second interlayer insulating layer to expose a significant portion of the second metal pattern;

forming a second trench in the first interlayer insulating layer using the second metal pattern as an etch mask to expose a significant portion of the first metal pattern;

forming a dielectric layer and a conductive layer on the sidewalls of the first and second interlayer insulating layers formed by the first and second trenches, and on the exposed significant portions of the first and second metal patterns; and

forming a third metal pattern on the dielectric layer and the conductive layer.

17. The method of claim 16 , wherein the dielectric layer and the conductive layer are conformally formed on the sidewalls of the first and second interlayer insulating layers and on the exposed significant portions of the first and second metal patterns.

18. The method of claim 16 , wherein the dielectric layer is sequentially formed on the conductive layer.

19. The method of claim 16 , further comprising:

forming a first metal interconnection with the first metal pattern; and,

forming a second metal interconnection with the second metal pattern.

20. The method of claim 16 , further comprising:

forming a second contact plug electrically connecting the first and second metal interconnections through the first interlayer insulating layer.

21. The method of claim 16 , further comprising:

forming a third metal interconnection on the second interlayer insulating layer.

22. The method of claim 17 , wherein the conductive layer is sequentially formed on the dielectric layer.

23. The method of claim 22 , wherein at least portions of the first and second metal patterns collectively comprise a capacitor lower electrode.

24. The method of claim 23 , further comprising:

forming at least one first contact plug electrically connecting the first and second metal patterns through the first interlayer insulating layer.

25. The method of claim 18 , wherein the conductive layer forms a capacitor lower electrode.

26. The method of claim 21 , further comprising:

forming a third contact plug electrically connecting the second and third metal interconnections through the second interlayer insulating layer.

27. The method of claim 26 , wherein the third contact plug is formed of the same material as the conductive layer.

28. A method for manufacturing a semiconductor device comprising:

forming a first metal interconnection and a first metal pattern on a substrate;

forming a first interlayer insulating layer on the first metal interconnection and the first metal pattern;

forming a second contact plug electrically connected with the first metal interconnection through the first interlayer insulating layer;

forming a second metal pattern having a first opening and a second metal interconnection electrically connected with the second contact plug;

forming a second interlayer insulating layer;

patterning the second interlayer insulating layer to form a first trench exposing the second metal pattern and a third contact hole exposing the second metal interconnection;

etching the first interlayer insulating layer exposed by the first opening using the exposed second metal pattern as an etch mask to form a second trench exposing the first metal pattern;

forming a conductive layer in the first and second trenches and in the third contact hole;

forming a dielectric layer in the first and second trenches;

forming a third metal pattern in the first and second trenches.

29. The method of claim 28 , wherein forming the dielectric layer and the conductive layer pattern comprises:

forming the dielectric layer in the first and the second trench;

forming a conductive layer on the dielectric layer such that it fills the third contact hole; and

performing a planarization process to remove any portion of the conductive layer outside the first and second trenches, and outside the third contact hole.

30. The method of claim 28 , wherein forming the dielectric layer and the conductive layer pattern comprises:

forming a conductive layer on the first and second trenches and filling the third contact hole;

performing a planarization process to remove any portion of the conductive layer outside the first and second trenches and outside the third contact hole to form a conductive layer pattern and a third contact plug; and

forming the dielectric layer on the conductive layer pattern.

31. The method of claim 28 , further comprising:

forming a first contact plug electrically connecting the first and second metal patterns through the first interlayer insulating layer outside the second trench.

32. The method of claim 28 , wherein forming the first trench and the third contact hole comprises:

forming a photoresist pattern having a second opening larger than the first opening and a third opening with substantially the same size as the third contact hole on the second interlayer insulating layer; and

etching the second interlayer insulating layer exposed by the second opening and the third opening.

33. A method for manufacturing a semiconductor device comprising:

simultaneously forming a first interconnection and a first metal pattern on a substrate;

forming a first interlayer insulating layer on the first metal interconnection and the first metal pattern;

simultaneously forming a second metal pattern having a first opening and a second metal interconnection;

forming a second interlayer insulating layer on the second metal pattern and the second metal interconnection;

patterning the second interlayer insulating layer to form a first trench exposing a significant portion of the second metal pattern and a third contact hole exposing the second metal interconnection;

etching a first interlayer insulating layer exposed by the first opening using the exposed second metal pattern as an etch mask to form a second trench exposing the first metal pattern;

forming a lower conductive layer conformally in the first and second trenches and filling the third contact hole;

forming a dielectric layer and an upper conductive layer on the lower conductive layer; and

planarizing the upper conductive layer, the dielectric layer and the lower conductive layer until the second interlayer insulating layer is exposed to form a metal-insulator-metal capacitor in the first and the second trench and a third contact plug in the third contact hole.

34. A semiconductor device comprising:

a first metal pattern formed on a substrate;

a first interlayer insulating layer including a second trench exposing the first metal pattern;

a second metal pattern disposed on a first interlayer insulating layer around the second trench;

a second interlayer insulating layer disposed on the first interlayer insulating layer and the second metal pattern and having a first trench exposing a part of the second metal pattern around the second trench;

a dielectric layer and a conductive layer formed on the sidewalls of the first and the second interlayer insulating layer in the first and the second trench and on the first and the second metal pattern; and

a third metal pattern formed on the dielectric layer, the conductive layer and the second interlayer insulating layer.