D flip-flop
A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.
1. A D flip-flop, comprising:
a master stage comprising a first data input line, a first clock line, a first data output line, and a storage circuit configured to store a signal applied at the first data input line;
a slave stage comprising a second data input line operatively connected to the first data output line, a second clock line and a second data output line, and further comprising:
a storage circuit; and
a first switching element configured to electrically connect the input terminal of the storage circuit to the second data input line in response to a state of clock signal present on the second clock line, and
a clock gating circuitry comprising
an XNOR gate having two inputs connected to the first data input line and second data output line, respectively, and an output;
a gating switching transistor having a gate connected to the output of the XNOR gate; and
a gating inverter having an input adapted to connect to an external source of clock pulses, and output connected to the first clock line, and an enable input connected to the switching transistor as a load.
2. The D flip-flop of claim 1 , wherein
the storage circuit of the slave stage comprising a first inverter having an input end connected to the input terminal and an output end connected to the second data output line, and a second switching element configured to electrically connect the input terminal of the storage circuit to a fixed output voltage source in response to a state of a signal at the second data output line, and
the slave stage being otherwise free of pull-down circuitry electrically connected to the input end of the first inverter.
3. The flip-flop of claim 2 , wherein the second switching element consists of a first switching transistor.
4. The flip-flop of claim 3 , wherein the first switching transistor comprises a gate connected to the second data output line, and a source-drain region linking the input end of the first inverter to the fixed output voltage source.
5. The flip-flop of claim 4 , wherein the first switching transistor is a PMOS transistor having a gate, drain and source, wherein one of the drain and source is connected to the input of the first inverter and the other of the drain and source is connected to a rail voltage supply, and the output of the first inverter is connected to the second data output line and to the gate of the PMOS transistor.
6. The flip-flop of claim 2 , wherein the first switching element consists of a second switching transistor.
7. The flip-flop of claim 6 , wherein the second switching transistor comprises a gate connected to the second clock line, and a source-drain region linking the input end of the first inverter to the second data input line.
8. The flip-flop of claim 2 , wherein the master stage comprises a dynamic flip-flop.
9. The flip-flop of claim 8 , wherein the dynamic flip-flop comprises a portion having a capacitance for storing a state of a signal at the first data output line.
10. The flip-flop of claim 8 , wherein the dynamic flip-flop comprises a second inverter having an input terminal operatively connected to the first data input line and output terminal connected to the first data output line.
11. The flip-flop of claim 10 , wherein the master stage further comprises a third switching transistor having a gate connected to the first clock line, and a source-drain region linking the first data input line to the input terminal of the second inverter.
12. The flip-flop of claim 10 , wherein the second inverter further comprises an enable input, the master stage further includes a driving circuitry having a control input and adapted to enable the second inverter via the enable input in response to a state of a signal at the control input.
13. The flip-flop of claim 12 , wherein the control input of the driving circuitry is adapted to receive a signal indicative of a signal at the first clock line.
14. The flip-flop of claim 13 , wherein the driving circuitry comprises a fourth switching transistor having a gate, and a source-drain region for driving the enable input of the second inverter, and the gate of the fourth switching transistor is operatively connected to the external clock.
15. The flip-flop of claim 14 , wherein the driving circuitry comprises a third inverter, the input of the third inverter is connected to the output of the gating inverter and the output of the third inverter is connected to the gate of the fourth switching transistor.
16. The flip-flop of claim 2 , wherein the second clock line is adapted to be connected to the external source of clock pulses.
17. A D flip-flop, comprising:
a master stage comprising a first data input line, a first clock line, a first data output line, and a first storage circuit configured to store a signal applied at the first data input line;
a slave stage comprising a second data input line operatively coupled to the first data output line and a second data output line; and
a clock gating circuitry comprising
an XNOR gate having two inputs coupled to the first data input line and second data output line, respectively, and an output;
a gating switching transistor having a gate coupled to the output of the XNOR gate; and
a gating inverter having an input adapted to couple to an external source of clock pulses, and an output coupled to the first clock line, and an enable input coupled to the switching transistor as a load.
18. The flip-flop of claim 17 , wherein the master stage further comprises a first inverter having an input terminal operatively coupled to the first data input line and output terminal coupled to the first data output line.
19. The flip-flop of claim 18 , wherein the master stage further comprises a first switching transistor having a gate coupled to the first clock line, and a source-drain region linking the first data input line to the input terminal of the first inverter.
20. The flip-flop of claim 19 , wherein the master stage further comprises a second switching transistor having a gate, and a source-drain region for driving the enable input of the first inverter, and the gate of the second switching transistor is operatively coupled to the external clock.
21. The flip-flop of claim 20 , wherein the master stage further comprises a second inverter, the input of the second inverter is coupled to the output of the gating inverter and the output of the second inverter is coupled to the gate of the second switching transistor.