Data coding system and method
View Patent ↗A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.
1. A data coding method comprising the steps of:
appending an extra bit to a data entry;
setting the extra bit to a first value responsive to a bit immediately preceding the extra bit being a don't care bit;
setting the extra bit to a second value responsive to the bit immediately preceding the extra bit not being a don't care bit, wherein the second value is distinct from the first value;
for each don't care bit in the data entry, setting the don't care bit to the first value responsive to a bit immediately preceding the don't care bit also being a don't care bit; and
for each don't care bit in the data entry, setting the don't care bit to the second value responsive to the bit immediately preceding the don't care bit not being a don't care bit.
2. The method of claim 1 , wherein the data entry comprises a prefix portion and a don't care portion, the don't care portion comprising a block of consecutive don't care bits appended to the prefix portion.
3. The method of claim 1 , wherein at least one bit in the data entry is not a don't care bit, the method further comprising comparing the at least one bit in the data entry that is not a don't care bit to at least one corresponding bit in an input entry.
4. The method of claim 1 , further comprising storing the coded data entry in a specification memory.
5. A method for decoding an encoded data entry to produce a decoded data entry, the method comprising the steps of:
receiving the encoded data entry having a first encoded bit at a first bit position and a second encoded bit at a second bit position, the second bit position immediately following the first bit position;
responsive to the second encoded bit having a first value, indicating that a bit in the decoded data entry at the first bit position is a don't care bit; and
responsive to the second encoded bit having a second value, indicating that the bit in the decoded data entry at the first bit position has a value equivalent to the first encoded bit.
6. The method of claim 5 , wherein at least one bit in the decoded data entry is not a don't care bit, the method further comprising comparing the at least one bit in the decoded data entry that is not a don't care bit to at least one corresponding bit in an input entry.
7. The method of claim 5 , wherein the second encoded bit is an extra bit appended to the encoded data entry.
8. The method of claim 7 , further comprising determining which bits in the encoded data entry are extra bits.
9. A computer program product for coding data, the computer program product stored on a computer-readable storage medium and including instructions that when executed cause a processor to carry out the steps of:
appending an extra bit to a data entry;
setting the extra bit to a first value responsive to a bit immediately preceding the extra bit being a don't care bit;
setting the extra bit to a second value responsive to the bit immediately preceding the extra bit not being a don't care bit, wherein the second value is distinct from the first value;
for each don't care bit in the data entry, setting the don't care bit to the first value responsive to a bit immediately preceding the don't care bit also being a don't care bit; and
for each don't care bit in the data entry, setting the don't care bit to the second value responsive to the bit immediately preceding the don't care bit not being a don't care bit.
10. The computer program product of claim 9 , wherein the data entry comprises a prefix portion and a don't care portion, the don't care portion comprising a block of consecutive don't care bits appended to the prefix portion.
11. The computer program product of claim 9 , wherein at least one bit in the data entry is not a don't care bit, the instructions when executed further cause the processor to compare the at least one bit in the data entry that is not a don't care bit to at least one corresponding bit in an input entry.
12. The computer program product of claim 9 , further comprising instructions for storing the coded data entry in a specification memory.
13. A computer program product for decoding an encoded data entry to produce a decoded data entry, the computer program product stored on a computer-readable storage medium and including instructions that when executed cause a processor to carry out the steps of:
receiving the encoded data entry having a first encoded bit at a first bit position and a second encoded bit at a second bit position, the second bit position immediately following the first bit position;
responsive to the second encoded bit having a first value, indicating that a bit in the decoded data entry at the first bit position is a don't care bit; and
responsive to the second encoded bit having a second value, indicating that the bit in the decoded data entry at the first bit position has a value equivalent to the first encoded bit.
14. The computer program product of claim 13 , wherein at least one bit in the decoded data entry is not a don't care bit, the instructions when executed further cause the processor to compare the at least one bit in the decoded data entry that is not a don't care bit to at least one corresponding bit in an input entry.
15. The computer program product of claim 13 , wherein the second encoded bit is an extra bit appended to the encoded data entry.
16. The computer program product of claim 15 , further comprising determining which bits in the encoded data entry are extra bits.
17. A system for decoding an encoded data entry to produce a decoded data entry, the system comprising:
a specification memory storing the encoded data entry having a first encoded bit at a first bit position and a second encoded bit at a second bit position, the second bit position immediately following the first bit position; and
an interpretation circuit coupled to the specification memory, the interpretation circuit receiving the encoded data entry and responsive to the second encoded bit having a first value, indicating that a bit in the decoded data entry at the first bit position is a don't care bit, and responsive to the second encoded bit having a second value, indicating that the bit in the decoded data entry at the first bit position has a value equivalent to the first encoded bit.
18. The system of claim 17 , wherein at least one bit in the decoded data entry is a don't care bit, the system further comprising a compare circuit comparing the at least one bit in the decoded data entry that is not a don't care bits to at least one corresponding bit in an input entry.
19. The system of claim 17 , wherein the second encoded bit is an extra bit appended to the encoded data entry.
20. The system of claim 19 , wherein the interpretation circuit further determines which bits in the encoded data entry are extra bits.