IP Library › Granted Patent US 7,407,859
Granted Patent B2
US 7,407,859 · App. 11/541,571 · Granted Aug 5, 2008

Compound semiconductor device and its manufacture

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,407,859
App. No.
11/541,571
Granted
Aug 5, 2008
Kind
B2
Abstract

A compound semiconductor device has: a substrate; a GaN channel layer; an n-type AlqGal-qN (0<q (1) electron supply layer; an n-type GaN cap layer; a gate electrode disposed on the cap layer and forming a Schottky contact; recesses formed on both sides of the gate electrode on source and drain sides by at least partially removing the cap layer, the recesses having a bottom surface of a roughness larger than a roughness of a surface of the cap layer under the gate electrode; a source electrode disposed on the bottom surface of the recess on the source side; and a drain electrode disposed on the bottom surface of the recess on the drain side.

Claims (9)

1. A method of manufacturing a compound semiconductor device comprising the steps of:

(a) epitaxially laminating above a substrate a channel layer consisting essentially of GaN, an electron supply layer consisting essentially of n-type AlqGal-qN (0<q (1) and a cap layer consisting essentially of n-type GaN, in this order recited;

(b) forming a gate electrode on said cap layer, said gate electrode having a Schottky contact;

(c) etching at least part of the cap layer to form recesses on both sides of said gate electrode on source and drain sides, in such a manner that a bottom surfaces of said recesses have a roughness larger than a roughness of a surface of said cap layer under said gate electrode; and

(d) forming a source electrode and a drain electrode on the bottom surfaces of said recesses on the source and drain sides.

2. The method of manufacturing a compound semiconductor device according to claim 1 , wherein said step (c) partially leaves said cap layer and partially exposes said electron supply layer by positively utilizing said roughness, and said step (d) forms one or both of said source and drain electrodes so as to make one or both contact both said cap layer and said electron supply layer.

3. The method of manufacturing a compound semiconductor device according to claim 1 , further comprising a step of exposing the surfaces of said recesses to plasma after said step (c).

4. The method of manufacturing a compound semiconductor device according to claim 1 , wherein said step (c) includes etching said recess on the source side by using a mask and etching said recess on the drain side by using another mask.

5. The method of manufacturing a compound semiconductor device according to claim 1 , further comprising a step of forming a notch through said cap layer, said notch traversing in a depth direction said cap layer at least between said gate electrode and said drain electrode or between said source electrode and said gate electrode.

Priority Claims (1)
JP 2003-017308 · Jan 27, 2003 · national
Continuity (2)
Division 1076448600 · Jan 27, 2004
Related Publication 20070026552A1 · Feb 1, 2007