IP Library › Granted Patent US 7,411,281
Granted Patent B2
US 7,411,281 · App. 10/870,928 · Granted Aug 12, 2008

Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same

Assignee: Broadcom Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,411,281
App. No.
10/870,928
Filed
Jun 21, 2004
Granted
Aug 12, 2008
Kind
B2
Examiner
TRINH, HOA B
Art Unit
2814
USPC
257/678
Abstract

Die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. A die-down array IC device package includes a heat spreader having a central cavity. A first substrate surface is coupled to the heat spreader. A central opening through the substrate overlaps the central cavity. Alternatively, the heat spreader is formed by coupling a ring-shaped body to a planar heat spreader. The first substrate surface is coupled to the ring-shaped body and the substrate central opening overlaps a central opening through the ring-shaped body. An array of electrically conductive terminals is coupled to a second substrate surface. An IC die is mounted to the heat spreader within the central cavity. Bond pads on the die are coupled to corresponding bond pads on the substrate with a plurality of wire bonds. Electrically conductive bumps on the die are coupled to corresponding bond pads on an interposer.

Claims (35)

1. A die-down array integrated circuit (IC) device package, comprising:

a heat spreader having opposing first and second surfaces, wherein said first surface of said heat spreader has a central cavity formed therein;

a substrate having a first surface coupled to said first surface of said heat spreader, and having an array of electrically conductive terminals on a second surface, wherein said substrate further has a central opening that is open at said first and second surfaces of said substrate, wherein said central opening overlaps said central cavity;

an IC die having a first surface mounted to said first surface of said heat spreader within said central cavity;

at least one wire bond that couples at least one bond pad on a second surface of said IC die to at least one bond pad on said second surface of said substrate; and

an interposer having opposing first and second surfaces, wherein a plurality of electrically conductive bumps on said second surface of said IC die is coupled to corresponding bond pads on said first surface of said interposer, wherein the interposer and the substrate are separate elements.

2. The die-down array IC device package of claim 1 , wherein said array of electrically conductive terminals and said second surface of said interposer are configured to surface mount the package to a printed circuit board (PCB).

3. The die-down array IC device package of claim 1 , wherein said second surface of said interposer has an array of electrically conductive terminals thereon, wherein said arrays of electrically conductive terminals on said second surfaces of said substrate and said interposer are configured to surface mount the package to a printed circuit board (PCB).

4. The die-down array IC device package of claim 3 , wherein said arrays of electrically conductive terminals on said second surfaces of said substrate and said interposer include an array of electrically conductive balls, pins, studs, or pads.

5. The die-down array IC device package of claim 1 , further comprising:

a heat slug having opposing first and second surfaces, wherein said first surface of said heat slug is coupled to said second surface of said interposer, wherein said array of electrically conductive terminals and said second surface of said heat slug are configured to surface the mount package to a printed circuit board (PCB).

6. The die-down array IC device package of claim 1 , wherein said at least one bond pad comprises a plurality of bond pads located on a peripheral area of said second surface of said IC die.

7. The die-down array IC device package of claim 1 , wherein said plurality of electrically conductive bumps is located on a central area of said second surface of said IC die.

8. The die-down array IC device package of claim 1 , wherein said first surface of said IC die is coupled to said first surface of said heat spreader with an adhesive material.

9. The die-down array IC device package of claim 1 , further comprising:

an encapsulating material, wherein said encapsulating material encapsulates said IC die and said at least one wire bond.

10. The die-down array IC device package of claim 1 , further comprising:

an underfill material that fills a space between said second surface of said IC die and said first surface of said interposer.

11. The die-down array IC device package 1 , wherein said heat spreader comprises:

a substantially planar body having opposing first and second surfaces, wherein said second surface of said substantially planar body comprises said second surface of said heat spreader; and

a ring-shaped body having a central opening that is open at a first surface and a second surface of said ring-shaped body, wherein said first surface of said ring-shaped body is coupled to said first surface of said substantially planar body, and wherein said second surface of said ring-shaped body comprises said first surface of said heat spreader;

wherein said central opening through said ring-shaped body and a portion of said first surface of said substantially planar body that is exposed through said central opening through said ring-shaped body form said central cavity.

12. The die-down array IC device package of claim 11 , wherein said array of electrically conductive terminals and said second surface of said interposer are configured to surface mount the package to a printed circuit board (PCB).

13. The die-down array IC device package of claim 11 , wherein said second surface of said interposer has an array of electrically conductive terminals thereon, wherein said arrays of electrically conductive terminals on said second surfaces of said substrate and said interposer are configured to surface mount the package to a printed circuit board (PCB).

14. The die-down array IC device package of claim 13 , wherein said arrays of electrically conductive terminals on said second surfaces of said substrate and said interposer include an array of electrically conductive balls, pins, studs, or pads.

15. The die-down array IC device package of claim 11 , further comprising:

a heat slug having opposing first and second surfaces, wherein said first surface of said heat slug is coupled to said second surface of said interposer, wherein said array of electrically conductive terminals and said second surface of said heat slug are configured to surface mount the package to a printed circuit board (PCB).

16. The die-down array IC device package of claim 11 , wherein said at least one bond pad comprises a plurality of bond pads located on a peripheral area of said second surface of said IC die.

17. The die-down array IC device package of claim 11 , wherein said plurality of electrically conductive bumps is located on a central area of said second surface of said IC die.

18. The die-down array IC device package of claim 11 , wherein said first surface of said IC die is coupled to said first surface of said heat spreader with an adhesive material.

19. The die-down array IC device package of claim 11 , wherein said first surface of said ring-shaped body is coupled to said first surface of said substantially planar body with an adhesive material.

20. The die-down array IC device package of claim 11 , further comprising:

an encapsulating material, wherein said encapsulating material encapsulates said IC die and said at least one wire bond.

21. The die-down array IC device package of claim 11 , further comprising:

an underfill material that fills a space between said second surface of said IC die and said first surface of said interposer.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2004
From: ZHANG, TONGLONG
To: BROADCOM CORPORATION
Reel/Frame 015524/0442 →
Continuity (1)
Related Publication 20050280141A1 · Dec 22, 2005