Semiconductor integrated circuit
A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
1. A semiconductor integrated circuit comprising:
a memory interface circuit;
a data processing circuit;
a clock generator; and
a memory controller coupled to said memory interface circuit and configured to perform access control on a double data rate type synchronous memory which outputs read data in synchronization with a data strobe signal,
wherein said memory interface circuit is configured to be coupled to the double data rate type synchronous memory,
wherein said clock generator generates an internal clock signal and a memory clock signal for supply to the double data rate type synchronous memory,
wherein said memory interface circuit determines an arrival delay of a data strobe signal received in a read cycle of the double data rate type synchronous memory relative to the internal clock signal, samples read data of the read cycle based on a signal obtained by shifting the phase of the received data strobe signal, and synchronizes the sampled read data to the internal clock signal based on a result of the determination of the arrival delay,
wherein said memory interface circuit is controlled by the memory controller to determine the arrival delay in the read cycle of the double data rate type synchronous memory, and
wherein the memory interface circuit is configured to provide the result of determination of the arrival delay to a synchronizing circuit of said memory interface circuit during a predetermined period in which no read cycle occurs with respect to the double data rate type synchronous memory.
2. The semiconductor integrated circuit according to claim 1 , wherein said memory interface circuit generates a dummy read cycle to determine the arrival delay when no read cycle occurs during a predetermined refresh interval of the double data rate type synchronous memory.
3. The semiconductor integrated circuit according to claim 1 , wherein said memory interface circuit generates a dummy read cycle to determine the arrival delay in response to a power-on reset.
4. The semiconductor integrated circuit according to claim 1 , wherein said predetermined period is a refresh cycle of the double data rate type synchronous memory.
5. The semiconductor integrated circuit according to claim 1 , wherein the read cycle to determine the arrival delay is carried out in a predetermined timing, arbitrarily determined based on a result of determination in another read cycle in which arrival delay previously has been determined.
6. A semiconductor integrated circuit comprising:
a memory interface circuit;
a data processing circuit;
a clock generator; and
a memory controller coupled to said memory interface circuit and configured to perform access control on a double data rate type synchronous memory which outputs read data in synchronization with a data strobe signal,
wherein said memory interface circuit is configured to be coupled to the double data rate type synchronous memory,
wherein said clock generator generates an internal clock signaTh and a memory clock signal for supply to the double data rate type synchronous memory,
wherein said memory interface circuit is configured to supply a test pulse to an external terminal to be coupled to a delay element which simulates a load of a transfer system of the memory clock signal, to determine a transfer delay of the memory clock signal to the double data rate type synchronous memory, to sample received read data based on a signal obtained by shifting the phase of a received data strobe signal, and to synchronize sampled read data to the internal clock signal based on a result of determination of the transfer delay, and
wherein a result of determination of the transfer delay is provided to a synchronizing circuit of said memory interface circuit during a predetermined period in which no read cycle occurs with respect to the double data rate type synchronous memory.
7. The semiconductor integrated circuit according to claim 6 , wherein said predetermined period is a refresh cycle of the double data rate type synchronous memory.