Core voltage generator and method for generating core voltage in semiconductor memory device
Provided are a core voltage generator and a method for generating a core voltage in a semiconductor memory device. The core voltage generator includes a first discharge driver for discharging a core voltage terminal for an interval at which the voltage is higher than a target level, in response to a first enable signal activated for a first predetermined period after overdriving a bit line, and a second discharge driver for discharging the core voltage terminal for an interval at which the voltage at the core voltage terminal is higher than the target level by a predetermined threshold, in response to a second enable signal activated for a second predetermined period after overdriving the bit line, wherein the second predetermined period is shorter than the first predetermined period.
1. A core voltage generator in a semiconductor memory device, comprising:
a first discharge driver for discharging a core voltage terminal for an interval during which the voltage at the core voltage terminal is higher than a target level, in response to a first enable signal activated for a first predetermined period after overdriving a bit line; and
a second discharge driver for discharging the core voltage terminal for an interval during which the voltage at the core voltage terminal is higher than the target level by a predetermined threshold, in response to a second enable signal activated for a second predetermined period after overdriving the bit line, wherein the second predetermined period is shorter than the first predetermined period,
wherein the first discharge driver and the second discharge driver simultaneously discharge the core voltage when the core voltage terminal is higher than the target level by the predetermined threshold.
2. The core voltage generator as recited in claim 1 , wherein the second discharge driver has a large driving power compared to the first discharge driver.
3. The core voltage generator as recited in claim 2 , wherein the first discharge driver includes:
a comparator for comparing a ½ level of the voltage at the core voltage terminal with ½ of the target level; and
a discharge driver for discharging the core voltage terminal in response to an output signal of the comparator.
4. The core voltage generator as recited in claim 1 , wherein the second discharge driver includes:
a comparator for comparing a ½ level of the voltage at the core voltage terminal with a ½ level of a core voltage rise limit voltage; and
a discharge driver for discharging the core voltage terminal in response to an output signal of the comparator.
5. A core voltage generator for use in a semiconductor memory device, comprising:
a first discharge driver for discharging a core voltage in response to a first enable signal; and
a second discharge driver for discharging the core voltage in response to a second enable signal,
wherein an active period of the second enable signal is shorter than an active period of the first enable signal,
wherein the first discharge driver and the second discharge driver simultaneously discharge the core voltage when the core voltage is higher than a target level by a predetermined threshold.
6. The core voltage generator as recited in claim 2 , wherein a driving force of the second discharge driver is greater than that of the first discharge driver.
7. A core voltage generator for use in a semiconductor memory device, comprising:
a first discharge driver for discharging a core voltage in response to a first enable signal, the first discharge driver comprising a first discharge transistor controlled by the first enable signal; and
a second discharge driver for discharging the core voltage in response to a second enable signal, the second discharge driver comprising a second discharge transistor controlled by the second enable signal,
wherein a size of the second discharge transistor is larger than that of the first discharge transistor,
wherein the first discharge driver and the second discharge driver simultaneously discharge the core voltage when the core voltage is higher than a target level by a predetermined threshold.
8. The core voltage generator as recited in claim 7 , wherein an active period of the second enable signal is shorter than that of the first enable signal.