Processing activity masking in a data processing system
A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not vary in dependence upon the data value being written or the previous data value.
1. Apparatus for processing data, said apparatus comprising:
a data processing register operable to store a data value;
a register writing circuit operable to store a data value to said data processing register; and
three or more further registers; wherein
when said register write circuit writes a data value to said data processing register, said register write circuit is configured to also write data values to three or more further registers such that the number of bits within said data processing register and said three or more further registers as a whole that transition from high to low equals the number of bits within said data processing register and said three or more further registers as a whole that transition from low to high irrespective of what data value is being written to said data processing register and what data value was previously stored within said data processing register.
2. Apparatus as claimed in claim 1 , wherein when said register write circuit writes a value X i to an i th bit of said data processing register previously storing a value of Y i , said register write circuit also writes to corresponding bit positions within three further registers respective values of:
an inverse of X i ;
a new value Rd i given by [(inverse (X i XOR Y i )) XOR (a value of Rd i currently stored in one of said three further registers)]; and
an inverse of said new value of Rd i .
3. Apparatus as claimed in claim 1 , wherein said data processing register is one of a plurality of data processing registers of a register bank.
4. Apparatus as claimed in claim 3 , wherein said three further registers comprise a dedicated dummy register dedicated to said data processing register and two shared dummy registers shared between said plurality of data processing registers of said register bank.
5. Apparatus as claimed in claim 4 , wherein when said register write circuit writes a value X i to an i th bit of said data processing register previously storing a value of Y i , said register write circuit also writes to corresponding bit positions within three further registers comprising a dedicated dummy register dedicated to said data processing register and two shared dummy registers shared between said plurality of data processing registers of said register bank such that said dedicated dummy register stores said inverse of X i and said two shared dummy registers store a new value Rd i given by [(inverse (X i XOR Y i )) XOR (a value of Rd i currently stored in one of said shared dummy registers)] and an inverse of said new value of Rd i .
6. Apparatus as claimed in claim 4 , wherein said three further registers are provided for a subset of said plurality of data processing registers of said register bank.
7. A method of processing data, said method comprising the steps of:
storing a data value in a data processing register; and
when said data value is stored in said data processing register also storing data values within three or more further registers such that the number of bits within said data processing register and said three or more further registers as a whole that transition from high to low equals the number of bits within said data processing register and said three or more further registers as a whole that transition from low to high irrespective of what said data value is being written to data processing register and what data value was previously stored within said data processing register.
8. A method as claimed in claim 7 , wherein when writing a value X i to an i th bit of said data processing register previously storing a value of Y i , also writing to corresponding bit positions within three further registers respective values of:
an inverse of X i ;
a new value Rd i given by [(inverse (X i XOR Y i )) XOR (a value of Rd i currently stored in one of said three further registers)]; and
an inverse of said new value of Rd i .
9. A method as claimed in claim 7 , wherein said data processing register is one of a plurality of data processing registers of a register bank.
10. A method as claimed in claim 9 , wherein said three further registers comprise a dedicated dummy register dedicated to said data processing register and two shared dummy registers shared between said plurality of data processing registers of said register bank.
11. A method as claimed in claim 10 , wherein when writing a value X i to an i th bit of said data processing register previously storing a value of Y i , also writing to corresponding bit positions within three further registers comprising a dedicated dummy register dedicated to said data processing register and two shared dummy registers shared between said plurality of data processing registers of said register bank such that said dedicated dummy register stores said inverse of X i and said two shared dummy registers store a new value Rd i given by [(inverse (X i XOR Y i )) XOR (a value of Rd i currently stored in one of said shared dummy registers)] and an inverse of said new value of Rd i .
12. A method as claimed in claim 10 , wherein said three further registers are provided for a subset of said plurality of data processing registers of said register bank.