IP Library › Granted Patent US 7,436,787
Granted Patent B2
US 7,436,787 · App. 10/904,453 · Granted Oct 14, 2008

Transceiver for full duplex communication systems

Assignee: Realtek Semiconductor Corp.
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Quick Facts
Patent No.
US 7,436,787
App. No.
10/904,453
Granted
Oct 14, 2008
Kind
B2
Abstract

A transceiver in a full duplex communication system includes a transmitting circuit coupled to a channel for transmitting a transmit signal to the channel, a cancellation signal generator coupled to the channel for generating a cancellation signal according to the transmit signal, and an echo cancellation device coupled to the transmitting circuit and the cancellation signal generator for attenuating an echo corresponding to the transmit signal with the cancellation signal.

Claims (35)

1. A transceiver in a full duplex communication system, the transceiver comprising:

a transmitting circuit coupled to a channel for transmitting a transmit signal to the channel;

a cancellation signal generator coupled to the channel for generating a cancellation signal according to the transmit signal, wherein the cancellation signal corresponds to the transmit signal;

a phase adjusting circuit coupled to the transmitting circuit and the cancellation signal generator for adjusting the phase of the cancellation signal, comprising:

a capacitor module including a plurality of capacitors coupled in parallel and a plurality of switches coupled to the corresponding capacitors respectively;

an echo residue detector coupled to the echo cancellation circuit for detecting an echo residue and generating a control signal according to the echo residue to control the switches of the capacitor module; and

an echo cancellation circuit coupled to the transmitting circuit and the cancellation signal generator for attenuating an echo corresponding to the transmit signal with the cancellation signal.

2. The transceiver of claim 1 , wherein the echo cancellation circuit comprises a gain amplifier.

3. The transceiver of claim 2 , wherein the gain amplifier is a programmable gain amplifier (PGA).

4. The transceiver of claim 1 , wherein the transmitting circuit comprises a digital-to-analog converter (DAC) for converting the transmit signal into an analog form.

5. A transceiver in a full duplex communication system, the transceiver comprising:

a transmitting circuit coupled to a channel for transmitting a transmit signal to the channel;

a cancellation signal generator coupled to the channel for generating a cancellation signal according to the transmit signal, wherein the cancellation signal corresponds to the transmit signal, comprising:

a current source for providing a current; a first output node and a second output node for outputting the cancellation signal, wherein the first output node is coupled to a first input terminal of the gain amplifier and the second output node is coupled to a second input terminal of the gain amplifier; a first switch coupled to the first output node and the current source; a second switch coupled to the second output node and the current source; a first resistor coupled to the first output node; a second resistor coupled to the second switch, wherein the cancellation signal is generated through controlling the first and the second switches; and an echo cancellation circuit coupled to the transmitting circuit and the cancellation signal generator for attenuating an echo corresponding to the transmit signal with the cancellation signal.

6. The transceiver of claim 5 , further comprising a phase adjusting circuit coupled to the transmitting circuit and the cancellation signal generator for adjusting the phase of the cancellation signal.

7. The transceiver of claim 6 , wherein the cancellation signal generator directly coupled to the echo cancellation circuit via the phase adjusting circuit.

8. A transceiver in a full duplex communication system, the transceiver comprising:

a transmitting circuit coupled to a channel for transmitting a transmit signal to the channel, comprising:

a digital-to-analog converter (DAC) for converting the transmit signal into an analog form, comprising:

a current source for providing a current;

a first output node and a second output node for outputting the transmit signal;

a first switch coupled to the first output node and the current source;

a second switch coupled to the second output node and the current source;

a first inductor coupled to the first output node;

a second inductor coupled to the second switch; and

a resistor coupled to the first and the second output node;

a cancellation signal generator coupled to the channel for generating a cancellation signal according to the transmit signal, wherein the cancellation signal corresponds to the transmit signal;

a phase adjusting circuit coupled to the transmitting circuit and the cancellation signal generator for adjusting the phase of the cancellation signal; and

an echo cancellation circuit coupled to the transmitting circuit and the phase adjusting circuit for attenuating an echo corresponding to the transmit signal with the cancellation signal.

9. The transceiver of claim 8 , further comprising:

an echo residue detector coupled to the echo cancellation circuit for detecting an echo residue and generating a control signal according to the echo residue to control the phase adjusting circuit.

10. The transceiver of claim 9 , wherein the phase adjusting circuit further comprises a capacitor module having a plurality of capacitors, and the control signal is employed to adjust the equivalent capacitance of the capacitor module.

11. The transceiver of claim 8 , wherein the echo cancellation circuit comprises a gain amplifier.

12. The transceiver of claim 11 , wherein the gain amplifier is a programmable gain amplifier (PGA).

13. The transceiver of claim 8 , wherein the cancellation signal generator is directly coupled to the echo cancellation circuit via the phase adjusting circuit.

Assignments (2)
CHANGE OF THE ADDRESS OF THE ASSIGNEE Recorded Sep 4, 2008
From: REALTEK SEMICONDUCTOR CORP.
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 021477/0570 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2004
From: HUANG, CHIH-WEN; CHEN, MU-JUNG
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 015359/0300 →
Priority Claims (1)
TW 93103106 A · Feb 10, 2004 · national
Continuity (2)
Continuation In Part 1090433800 · Nov 4, 2004
Related Publication 20050185603A1 · Aug 25, 2005