Automated processor generation system and method for designing a configurable processor
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
1. A system for designing a configurable processor, the system comprising:
hardware generation means for, based on a configuration specification including a predetermined portion and a user-defined portion, generating a description of a hardware implementation of the processor; and
software generation means for, based on the configuration specification, generating software development tools specific to the hardware implementation;
wherein the user-defined portion of the configuration specification includes scheduling information for one or more instructions executed by the processor;
and wherein the hardware generation means includes means for, based on the scheduling information, determining whether and how to generate a description of the logic of at least one pipeline stage and pipeline stalling logic for inclusion in the description of the hardware implementation of the processor.
2. The system of claim 1 , wherein the scheduling information includes a statement that an operand of an instruction enters a pipeline of the processor at a given stage.
3. The system of claim 1 , wherein the scheduling information includes a statement that an operation of an instruction exits a pipeline of the processor at a given stage.
4. The system of claim 1 , wherein:
the software generated by the software generation means includes a compiler which uses instructions described in the user-defined portion of the configuration specification; and
the compiler uses the scheduling information during instruction scheduling to schedule the instructions described in the user-defined portion of the configuration specification.
5. The system of claim 1 , wherein the configuration specification includes a description of an instruction which requires a plurality of processor cycles to be processed.
6. The system of claim 5 , wherein:
the user-defined portion of the configuration specification includes a description of an Instruction's semantics, the description of the instruction's semantics being independent of a description of a target pipeline for the instruction; and
the hardware generation means includes means for generating, for inclusion in the description of the processor hardware implementation, logic consistent with the target pipeline based on the configuration specification.
7. The system of claim 1 , wherein the scheduling information includes the number of execution stages for the instruction(s).
8. The system of claim 7 , wherein the hardware generation means includes means for determining a number of pipeline registers consistent with the number of specified execution stages to include in the description of the processor hardware implementation.
9. The system of claim 1 , wherein:
the software generated by the software generation means includes a compiler which uses instructions described in the user-defined portion of the configuration specification; and
the compiler uses the scheduling information during instruction scheduling to schedule the instructions to match a target pipeline in the generated description of the hardware implementation.
10. The system of claim 1 , wherein the hardware generation means includes means for generating, for inclusion in the description of the hardware implementation of the processor, interlock logic for accessing a register file of the processor.
11. The system of claim 10 , wherein the means for generating the interlock logic generates the interlock logic based on the scheduling information in the configuration specification.
12. The system of claim 10 , wherein the means for generating the interlock logic generates the interlock logic for a given pipeline of the processor described by the configuration specification based on instruction operand and state usage descriptions in the scheduling information.
13. A method for designing a configurable processor, the method comprising:
based on a configuration specification including a predetermined portion and a user-defined portion, generating a description of a hardware implementation of the processor; and
further based on the configuration specification, generating software development tools specific to the hardware implementation;
wherein the user-defined portion of the configuration specification includes scheduling information for one or more instructions executed by the processor;
and wherein the step of generating the hardware description includes, based on the scheduling information, determining whether and how to generate a description of the logic of at least one pipeline stage and pipeline stalling logic for inclusion in the description of the hardware implementation of the processor.
14. The method of claim 13 , wherein the scheduling information includes a statement that an operand of an instruction enters a pipeline of the processor at a given stage.
15. The method of claim 13 , wherein the scheduling information includes a statement that an operation of an instruction exits a pipeline of the processor at a given stage.
16. The method of claim 13 , wherein:
the generated software includes a compiler which uses instructions described in the user-defined portion of the configuration specification; and
the compiler uses the scheduling information during instruction scheduling to schedule the instructions described in the user-defined portion of the configuration specification.
17. The method of claim 13 , wherein the configuration specification includes a description of an instruction which requires a plurality of processor cycles to be processed.
18. The method of claim 17 , wherein:
the user-defined portion of the configuration specification includes a description of an Instruction's semantics, the description of the instruction's semantics being independent of a description of a target pipeline for the instruction; and
the step of generating the hardware description includes generating, for inclusion in the description of the processor hardware implementation, logic consistent with the target pipeline based on the configuration specification.
19. The method of claim 13 , wherein the scheduling information includes the number of execution stages for the instruction(s).
20. The method of claim 19 , wherein the step of generating the hardware description includes determining a number of pipeline registers consistent with the number of specified execution stages to include in the description of the processor hardware implementation.
21. The method of claim 13 , wherein:
the software generated by the software generation means includes a compiler which uses instructions described in the user-defined portion of the configuration specification; and
the compiler uses the scheduling information during instruction scheduling to schedule the instructions to match a target pipeline in the generated description of the hardware implementation of the processor.
22. The method of claim 13 , wherein the step of generating the hardware description includes generating, for inclusion in the description of the hardware implementation of the processor, interlock logic for accessing a register file of the processor.
23. The method of claim 22 , wherein the step of generating the interlock logic includes generating the interlock logic based on the scheduling information in the configuration specification.
24. The method of claim 22 , wherein the step of generating the interlock logic includes generating the interlock logic for a given pipeline of the processor described by the configuration specification based on instruction operand and state usage descriptions in the scheduling information.