Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films

1. A method of forming a layer of high-k dielectric gate oxide in an integrated circuit comprising:

preparing a silicon substrate, including forming an H-terminated surface on the silicon substrate;

forming a high-k dielectric layer by a sequence of ALD cycles and elevated temperature annealing including:

depositing a first layer of metal ligand by an ALD cycle with a metal nitrate precursor to form a metal oxide layer; and

depositing a second layer of metal ligand by ALD cycle with a non-oxygen containing metal chloride precursor to form a metal oxide layer;

repeating said depositing a first layer of metal ligand and said depositing a second layer of metal ligand N times to form a layer of metal oxide having a near-critical thickness;

annealing the substrate and the metal oxide layers in an elevated temperature annealing process every N ALD cycles;

repeating the sequence of ALD cycles and elevated temperature annealing until a high-k dielectric metal oxide layer of desired thickness is formed;

annealing the structure in a final annealing step; and

completing the integrated circuit.

2. The method of claim 1 which includes selecting a metal oxide taken from the group of metal oxides consisting of HfO 2 , ZrO 2 , Gd 2 O 3 , La 2 O 3 , CeO 2 , TiO 2 , Y 2 O 3 , Ta 2 O 5 , Al 2 O 3 , HfAlO x , ZrAlO x , LaO x , and combinations thereof, to be deposited on the silicon substrate.

3. The method of claim 1 wherein said depositing a first layer of metal ligand includes depositing an initial layer of metal oxide having a thickness of between less than a monolayer to about 2.5 nm, and wherein said depositing a second layer of metal ligand includes depositing a layer of metal oxide having a thickness of between less than a monolayer to about 2.5 nm.

4. The method of claim 1 wherein said annealing the substrate and the first and second metal oxide layers includes annealing at a temperature of between about 300° C. to 850° C. for between about one second to five minutes to remove excess ligands from a just-deposited layer before ligand buildup is too great for removal during a post-deposition anneal.

5. The method of claim 1 wherein said final annealing step includes annealing at a temperature of between about 400° C. to 1000° C. for between about one second to ten minutes.

6. The method of claim 1 wherein said depositing a first layer of metal ligand and said depositing a second layer of metal ligand includes depositing a layer using an ALD cycle having a pulse duration of between about 0.1 seconds to 100 seconds at a substrate temperature of between about 150° C. to 190° C.

7. The method of claim 1 wherein a near-critical thickness is that thickness where excess ligands may be efficiently removed before their buildup is so great that they can not be all removed by in the final annealing step.

8. A method of forming a layer of HfO 2 high-k dielectric gate oxide in an integrated circuit comprising:

preparing a silicon substrate, including forming an H-terminated surface on the silicon substrate;

forming a high-k dielectric layer by a sequence of ALD cycles including:

depositing a first layer of HfO 2 using an ALD cycle with a Hf(NO 3 ) 4 precursor to form a metal oxide layer; and

depositing a second layer of HfO 2 using an ALD cycle with a HfCl 4 precursor to form a metal oxide layer;

wherein said depositing a first layer of metal ligand and said depositing a second layer of metal ligand includes depositing a layer using an ALD cycle having a pulse duration of between about 0.1 seconds to 100 seconds at a substrate temperature of between about 150° C. to 190° C.;

repeating said depositing a first layer of metal ligand and said depositing a second layer of metal ligand N times to form a layer of metal oxide having a near-critical thickness, wherein a near-critical thickness is that thickness where excess ligands may be efficiently removed before their buildup is so great that they can not be all removed by in the final annealing step;

annealing the substrate and the metal oxide layers in an elevated temperature annealing process every N ALD cycles at a temperature of between about 300° C. to 850° C. for between about one second to five minutes to remove excess ligands from a just-deposited layer before ligand buildup is too great for removal during a post-deposition anneal;

repeating the sequence of ALD cycles and elevated temperature annealing until a high-k dielectric metal oxide layer of desired thickness is formed;

annealing the structure having the HfO 2 layer of desired thickness thereon in a final annealing process a temperature of between about 400° C. to 1000° C. for between about one second to ten minutes; and

completing the integrated circuit.

9. The method of claim 8 which includes selecting a metal oxide taken from the group of metal oxides consisting of HfO 2 , ZrO 2 , Gd 2 O 3 , La 2 O 3 , CeO 2 , TiO 2 , Y 2 O 3 , Ta 2 O 5 , Al 2 O 3 , HfAlO x , ZrAlO x , LaO x , and combinations thereof, to be deposited on the silicon substrate.

10. The method of claim 8 wherein said depositing a first layer of metal ligand includes depositing an initial layer of metal oxide having a thickness of between less than a monolayer to about 2.5 nm, and wherein said depositing a second layer of metal ligand includes depositing a layer of metal oxide having a thickness of between less than a monolayer to about 2.5 nm.