IP Library Granted Patent US 7,446,263
Granted Patent B2
US 7,446,263 · App. 10/864,400 · Granted Nov 4, 2008

Multilayer printed circuit board

Assignee: Ibiden Co., Ltd.
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Quick Facts
Patent No.
US 7,446,263
App. No.
10/864,400
Granted
Nov 4, 2008
Kind
B2
Abstract

The objective of present invention is to provide an electroplating solution capable of forming the upper face of a via-hole and the upper face of a conductor circuit in the same layer in approximately the same plane at the time of manufacturing a multilayer printed circuit board. The electroplating solution of the present invention is characterized by containing 50 to 300 g/L of copper sulfate, 30 to 200 g/L of sulfuric acid, 25 to 90 mg/L of chlorine ion, and 1 to 1000 mg/L of an additive comprising at least a levelling agent and a brightener.

Claims (12)

1. A multilayer printed circuit board comprising a substrate;

a first conductor circuit formed on the substrate;

a first resin insulating layer having an opening for a via-hole, the first resin insulating layer being formed on the substrate and the first conductor circuit;

a second conductor circuit formed on the first resin insulating layer;

a via-hole connecting the first conductor circuit and the second conductor circuit, the via-hole being a filled via;

a second resin insulating layer formed on the second conductor circuit, the filled via and the first resin insulating layer;

a third conductor circuit formed on the second resin insulating layer,

wherein the second conductor circuit and the filled via comprise an electroless plating film having a thickness which is from 0.1 to 5 μm and an electroplating film having a thickness which is from 3 to 25 μm on the electroless plating film, the filled via comprises the electroless plating film and the electroplating film filling the opening, an entire upper face of the filled via is substantially flat, the upper face of the filled via and an upper face of the second conductor circuit are kept approximately in the same plane, and a distance from a bottom face to the upper face of the filled via is about 2 to 7 times as long as the thickness of the second conductor circuit.

2. The multilayer printed circuit board according to claim 1 , wherein the first resin insulating layer and the second resin insulating layer have a dielectric constant of 3.0 or lower at 1 GHz.

3. The multilayer printed circuit board according to claim 1 ,

wherein a via-hole in an upper layer is disposed immediately over a via-hole in a lower layer.

4. The multilayer printed circuit board according to claim 1 , wherein a thickness of the electroplating film is 5 to 15 μm.

Priority Claims (5)
JP 11/224143 · Aug 6, 1999 · national
JP 2000/156877 · May 26, 2000 · national
JP 2000/156878 · May 26, 2000 · national
JP 2000/194619 · Jun 28, 2000 · national
JP 2000/194620 · Jun 28, 2000 · national
Continuity (2)
Division 1004885200
Related Publication 20040226745A1 · Nov 18, 2004