Method for refreshing a non-volatile memory
A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.
1. A method for refreshing a non-volatile memory, wherein the method comprises:
providing a non-volatile memory that allows an external system to control refreshing operations within the memory.
transmitting a refresh request signal to the external system; and
receiving a refresh acknowledge signal from the external system and responsively refreshing the memory.
2. The method as in claim 1 , wherein the memory comprises a refresh state machine for transmitting the refresh request signal and receiving the refresh acknowledge signal.
3. The method as in claim 2 , wherein the memory comprises at least one of a power-on reset detector, a refresh counter, and a threshold drift detector for triggering the state machine to transmit the refresh request signal.
4. The method as in claim 1 , wherein refreshing the memory comprises using a page register to read a data state from the memory and re-write the data state back to the memory.
5. The method as in claim 4 , wherein the page register comprises a plurality of latches.
6. A method for refreshing a non-volatile memory, the method comprising:
providing a non-volatile memory that comprises a controller, at least one memory page, and a page register;
the controller receiving a refresh acknowledge signal from an external system; and
responsive to receiving the refresh acknowledge signal, the controller directing the page register to read a data state associated with the memory page and rewrite the data state back to the memory.
7. The method as in claim 6 , further comprising the controller transmitting a refresh request signal to the external system and awaiting the refresh acknowledge signal.
8. The method as in claim 7 , wherein the controller comprises a refresh state machine for coordinating the refresh request and the refresh acknowledge signals.
9. The method as in claim 8 , wherein the refresh request signal is triggered by at least one of a threshold drift detector, a power-on reset detector, and a refresh counter.
10. The method as in claim 7 , further comprising the controller transmitting a refresh busy signal to the external system when the page register reads and rewrites the data state.
11. The method as in claim 6 , further comprising the controller using a page counter to refresh each memory page within the memory.
12. The method as in claim 6 , wherein the page register comprises a plurality of latches.
13. The method as in claim 12 , wherein the read of the data state further comprises using the plurality of latches to temporarily store the data state.
14. The method as in claim 13 , wherein the rewrite of the data state further comprises using the plurality of latches to write the temporarily stored data state back to the memory page.
15. A refreshable non-volatile memory, comprising:
at least one memory page that includes a plurality of non-volatile memory cells;
a decoder for selecting a memory page from the memory that is to be refreshed;
a page register that includes a plurality of latches for coupling to a selected memory page; and
a controller coupled to the page register and configured to receive a refresh acknowledge signal from an external system, wherein, in operation and upon receiving the refresh acknowledge signal, the controller directs the page register to read a data state associated with the selected memory page and rewrite the data state back to the selected memory page.
16. The memory as in claim 15 , wherein the controller comprises a refresh state machine for transmitting a refresh request signal to the external system.
17. The memory as in claim 16 , wherein the refresh state machine is configured to await the refresh acknowledge signal before reading and rewriting the data state back to the selected memory page.
18. The memory as in claim 16 , further comprising a threshold drift detector, a power-on reset detector, and a refresh counter for triggering the refresh state machine to transmit the refresh request signal.
19. The memory as in claim 16 , wherein the refresh state machine is configured to output a refresh busy signal to the external system when the memory page is being read and rewritten.
20. The memory as in claim 15 , wherein the first plurality of memory cells comprise a plurality of electrically erasable programmable read only memory cells.