Method of leakage optimization in integrated circuit design

1. A method of reducing leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells for particular circuit functions, the library including a plurality of cells for each circuit function, comprising the steps of:

considering design cells in a predetermined order;

for each considered design cell determining if said design cell had a timing slack greater than a predetermined slack limit;

for each design cell determined to have said timing slack, determining if said design cell has an output slew rate less than a slew limit;

for each design cell determined to have said output slew rate, determining all candidate cells in said library having the function of said design cell;

for all candidate cells for each design cell determining eligible candidate cells which have a size no greater than said design cell, timing slack less than a predetermined slack limit, output slew less than a predetermined output slew limit and leakage current less than said design cell;

for each design cell selecting a candidate cell having the least leakage current; and

substituting said candidate cell having the least leakage current for said design cell.

2. The method of claim 1 , wherein:

said predetermined order of considering design cells consists of traversing from design cells having the least number of cells in a timing path from a start point to an end point towards design cells having the greatest number cells in a timing path from the start point to the end point.

3. The method of claim 1 , wherein:

said predetermined order of considering design cells consists of traversing from design cells having the least number of cells in a timing path from an end point to start point towards design cells having the greatest number cells in a timing path from the end point to the start point.

4. The method of claim 1 , wherein:

said predetermined order of considering design cells consists of traversing from design cells having the least number of cells of timing paths passing through said design cell towards design cells having the greatest number timing paths passing through said design cell.

5. The method of claim 1 , wherein:

said predetermined order of considering design cells consists of traversing from design cells having the greatest output slew rate towards design cells having the least output slew rate.

6. The method of claim 1 , wherein:

said predetermined slack limit is selected to provide more time slack than needed for any timing path of design cells to meet its timing goal.

7. The method of claim 1 , wherein:

said library of cells includes for at least one function cells having differing transistor voltage thresholds; and

said step of selecting a candidate cell having the least leakage current includes selecting a candidate cell having a preferred voltage threshold.