IP Library Granted Patent US 7,449,912
Granted Patent B2
US 7,449,912 · App. 11/627,730 · Granted Nov 11, 2008

Fault detection circuit

Assignee: Hewlett-Packard Development Company, L.P.
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Quick Facts
Patent No.
US 7,449,912
App. No.
11/627,730
Granted
Nov 11, 2008
Kind
B2
Abstract

Power supplies are disclosed herein. One embodiment of a power supply comprises a first input and a second input, wherein the first input and the second input are connectable to a pulse width modulation controller and wherein a pulse width modulation signal is outputable from the pulse width modulation controller. A power stage connected to the first input and the second input. A first comparator having a first comparator first input is connected to the first input and a first comparator second input connected to the output of the power stage. A change of voltage at the output of the first comparator constitutes a difference in phase between the first input and the output of the power stage.

Claims (30)

1. A power supply comprising:

a first input;

a second input, wherein said first input and said second input are connectable to a pulse width modulation controller, wherein a pulse width modulation signal is outputable from said pulse width modulation controller;

a power stage connected to said first input and said second input, said power stage having an output;

a first comparator having a first comparator first input connected to said first input and a first comparator second input connected to said output of said power stage, wherein a change of voltage at the output of said first comparator constitutes a difference in phase between said first input and said output of said power stage.

2. The power supply of claim 1 , wherein said first comparator is an exclusive OR gate.

3. The power supply of claim 1 and further comprising a sample and hold circuit connected to said output of said first comparator.

4. The power supply of claim 1 and further comprising a second comparator having a second comparator first input connected to said second input and a second comparator second input connected to said output of said power stage, wherein a change of voltage at the output of said second comparator constitutes a difference in phase between said second input and said output of said power stage.

5. The power supply of claim 4 and further comprising a third comparator wherein said output of said first comparator and said output of said second comparator are connected to inputs of said third comparator; and wherein a voltage transition of either said output of said first comparator or the output of said second comparator causes a voltage transition at the output of said third comparator.

6. The circuit of claim 5 , wherein said third comparator is a gate.

7. The circuit of claim 5 and further comprising a sample and hold circuit connected to the output of said third comparator.

8. A power supply comprising:

a first input;

a second input, wherein said first input and said second input are connectable to a pulse width modulation controller, wherein a pulse width modulation signal is outputable from said pulse width modulation controller;

a power stage connected to said first input and said second input, said power stage having an output;

a first gate, wherein a first input of said first gate is connected to said first input, wherein a second input of said first gate is connected to said output of said power stage, wherein a voltage transition at the output of the first gate represents a fault with the power supply.

9. The power supply of claim 8 , wherein said first gate is an exclusive NOR gate.

10. The power supply of claim 8 and further comprising a second gate, wherein a first input of said second gate is connected to said second input, wherein a second input of said second gate is connected to said output of said power stage, wherein a voltage transition at the output of the second gate represents a fault with the power supply.

11. The power supply of claim 10 and further comprising an inverter connected between said second input and said first input of said second gate.

12. The power supply of claim 10 , wherein said second gate is an exclusive NOR gate.

13. The power supply of claim 10 and further comprising a third gate, wherein a first of input of said third gate is connected to said output of said first gate, wherein a second input of said third gate is connected to said output of said second gate, and wherein a voltage transition at the output of said third gate represents a fault with said power supply.

14. The power supply of claim 13 , wherein said third gate is a NOR gate.

15. The power supply of claim 13 and further comprising a sample and hold circuit connected to said output of said third gate.

16. A method of detecting a fault in a pulse width modulation type power supply, wherein said power supply is connectable to a pulse width modulation controler and wherein said pulse width modulation signal is connected to a power stage, said method comprising:

comparing the phase of a first input from the pulse width modulation controller to the output of the power stage; and

outputting a first voltage if the phase of said first input differs from the phase of said output of said power stage.

17. The method of claim 16 and further comprising:

comparing the phase of a second input from the pulse width modulation controller to the output of the power stage; and

outputting a second voltage if the phase of said second input differs from the phase of said output of said power stage.

18. The method of claim 17 and further comprising outputting a third voltage if either said first voltage or said second voltage is output.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2007
From: PRACHT, KELLY JEAN; BABB, SAMUEL M.; LAVIER, JACK
To: HEWLETT-PACKARD DEVELOPMENT, L.P.
Reel/Frame 019125/0023 →
Continuity (1)
Related Publication 20080180108A1 · Jul 31, 2008