LVDS input circuit with connection to input of output driver
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.
1. An LVDS signaling device, comprising:
A. a first LVDS signal path;
B. a second LVDS signal path;
C. an LVDS driver having a non-inverting output connected to the first LVDS signal path, an inverting output connected to the second LVDS signal path, and a data input lead;
D. a first resistor connected in series between the non-inverting output and the first LVDS signal path;
E. a second resistor connected in series between the inverting output and the second LVDS signal path;
F. a third resistor connected between the first and second LVDS signal paths; and
C. an input circuit having one non-inverting input that is connected to the first LVDS signal path, one inverting input that is connected to the second LVDS signal path, a data output and one input lead connected to the data input lead of the LVDS driver.
2. The device of claim 1 including:
A. another LVDS signaling device including:
i. another LVDS driver having a non-inverting output connected to the first LVDS signal path, an inverting output connected to the second LVDS signal path, and a data input;
ii. another first resistor connected in series between the non-inverting output and the first LVDS signal path;
iii. another second resistor connected in series between the inverting output and the second LVDS signal path;
iv. another third resistor connected between the first and second LVDS signal paths; and
v. another input circuit having one non-inverting input that is connected to the first LVDS signal path, one inverting input that is connected to the second LVDS signal path, a data output and an input connected to the data input of the another LVDS driver; and
B. a fourth resistor connected between the first and second LVDS signal paths.
3. The device of claim 1 including:
i. clock output circuitry having a data output;
ii. clock driver circuitry having a data input connected to the data output, a non-inverting output, and an inverting output;
iii. a third LVDS signal path connected to the non-inverting output; and
iv. a fourth LVDS signal path connected to the inverting output.
4. The device of claim 1 including:
i. a third LVDS signal path;
ii. a fourth LVDS signal path;
iii. clock receiver circuitry having a non-inverting input connected to the third LVDS signal path, an inverting input connected to the fourth LVDS signal path, and a data output;
iv. clock input circuitry having a data input connected to the data output; and
v. a fourth resistor connected between the third and fourth LVDS signal paths.