IP Library › Granted Patent US 7,453,329
Granted Patent B2
US 7,453,329 · App. 11/902,065 · Granted Nov 18, 2008

Variable attenuator and integrated circuit

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,453,329
App. No.
11/902,065
Granted
Nov 18, 2008
Kind
B2
Abstract

In a variable attenuator attenuating a signal inputted to an input terminal from a plurality of transmission lines connected in series between the input terminal and an output terminal and outputting the signal from the output terminal, first and second resistance elements to improve an input/output characteristic are connected in parallel respectively to the transmission line connected to the input terminal and the transmission line connected to the output terminal, so that reflection in input/output is sustained by the first and second resistance elements, to obtain a good input/output characteristic, and so that an impedance in a signal line is increased at a time of maximum attenuation without being suppressed by the first and second resistance elements, to obtain a large attenuation amount.

Claims (28)

1. A variable attenuator comprising:

a plurality of quarter wavelength transmission lines connected in series between an input terminal and an output terminal;

a plurality of transistors provided in correspondence with interconnection points between said plurality of transmission lines, in each of said transistor a drain being connected to the interconnection point of said transmission lines, a source being earthed, and control voltage being supplied to a gate;

a first resistance element connected in parallel to said transmission line connected to the input terminal; and

a second resistance element connected in parallel to said transmission line connected to the output terminal.

2. An integrated circuit comprising:

a semiconductor substrate on which an active element of the variable attenuator according to claim 1 is integrated; and

an insulating substrate on which a passive element of the variable attenuator is integrated.

3. An integrated circuit wherein each circuit element constituting the variable attenuator according to claim 1 is monolithically integrated on the same semiconductor substrate.

4. The variable attenuator according to claim 1 , wherein at least one of said first resistance element and said second resistance element is a variable resistance element.

5. The variable attenuator according to claim 4 , wherein said variable resistance element is constituted using a transistor.

6. The variable attenuator according to claim 4 , wherein said variable resistance element is constituted using an HEMT (high electron mobility transistor).

7. The variable attenuator according to claim 4 , wherein said variable resistance element is constituted using an HBT (hetero-junction bipolar transistor).

8. An integrated circuit comprising:

a transmission side mixer converting an intermediate frequency signal to a high frequency signal;

a transmission side variable attenuator of which an attenuation amount is adjustable and which attenuates and outputs the high frequency signal outputted from said transmission side mixer; and

a transmission side amplifier amplifying and outputting to an antenna the high frequency signal outputted from said transmission side variable attenuator,

wherein said transmission side variable attenuator includes a plurality of quarter wavelength transmission lines connected in series between an input terminal and an output terminal, a plurality of transistors provided in correspondence with interconnection points between said plurality of transmission lines, in each of said transistor a drain being connected to the interconnection point of said transmission lines, a source being earthed, and control voltage being supplied to a gate, a first resistance element connected in parallel to the transmission line connected to the input terminal, and a second resistance element connected in parallel to the transmission line connected to the output terminal.

9. The integrated circuit according to claim 8 , comprising:

a reception side amplifier supplied with a high frequency signal received by the antenna, and amplifying and outputting the high frequency signal;

a reception side variable attenuator of which an attenuation amount is adjustable and which attenuates and outputs a local oscillation signal; and

a reception side mixer converting the high frequency signal outputted from the reception side amplifier to an intermediate frequency signal, based on the local oscillation signal outputted from said reception side variable attenuator,

wherein said reception side variable attenuator includes a plurality of quarter wavelength transmission lines connected in series between an input terminal and an output terminal, a plurality of transistors provided in correspondence with interconnection points between said plurality of transmission lines, in each of said transistor a drain being connected to the interconnection point of said transmission lines, a source being earthed, and control voltage being supplied to a gate, a first resistance element connected in parallel to the transmission line connected to the input terminal, and a second resistance element connected in parallel to the transmission line connected to the output terminal.

10. An integrated circuit comprising:

a reception side amplifier supplied with a high frequency signal received by an antenna, and amplifying and outputting the high frequency signal;

a reception side variable attenuator of which an attenuation amount is adjustable and which attenuates and outputs a local oscillation signal; and

a reception side mixer converting the high frequency signal outputted from the reception side amplifier to an intermediate frequency signal, based on the local oscillation signal outputted from said reception side variable attenuator,

wherein said reception side variable attenuator includes a plurality of quarter wavelength transmission lines connected in series between an input terminal and an output terminal, a plurality of transistors provided in correspondence with interconnection points between said plurality of transmission lines, in each of said transistor a drain being connected to the interconnection point of said transmission lines, a source being earthed, and control voltage being supplied to a gate, a first resistance element connected in parallel to the transmission line connected to the input terminal, and a second resistance element connected in parallel to the transmission line connected to the output terminal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2007
From: INOUE, YUSUKE
To: FUJITSU LIMITED
Reel/Frame 020017/0358 →
Continuity (2)
Continuation PCTJP200500498600 · Mar 18, 2005
Related Publication 20080032653A1 · Feb 7, 2008