Variable width offset spacers for mixed signal and system on chip devices
View Patent ↗MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.
1. A method for forming multiple width offset spacers adjacent respective MOSFET gate structures comprising the steps of:
providing a semiconductor substrate comprising at least two gate structures;
growing a silicon oxide layer having a respective differential thickness over the at least two gate structures;
forming a dielectric layer on the silicon oxide layer having an etching selectivity with respect to the silicon oxide layer;
forming offset spacers having a differential thickness comprising the dielectric layer and the silicon oxide layer adjacent either side of the at least two respective gate structures; and,
carrying out an ion implant process adjacent the offset spacers to form doped regions in the semiconductor substrate to form at least two MOSFET devices, wherein the differential thickness comprises a relatively thicker and a relatively thinner silicon oxide layer, the relatively thinner silicon oxide layer is formed in a digital MOSFET device, a logic MOSFET device or an PMOS SRAM cell MOSFET device, and the relatively thicker silicon oxide layer is formed in an analog MOSFET device, an SRAM MOSFET device, or a NMOS SRAM cell MOSFET device.
2. The method of claim 1 , wherein the step of growing a silicon oxide layer comprises a prior step of ion implanting at least one of the at least two different respective gate structures with an ion having a property selected from the group consisting of enhancing silicon oxide growth and suppressing silicon oxide growth.
3. The method of claim 2 , wherein the step of ion implanting comprises an ion selected from the group consisting of nitrogen and fluorine ions.
4. The method of claim 1 , wherein the differential thickness comprises a relatively thicker and a relatively thinner silicon oxide layer, and the relatively thicker silicon oxide layer has a thickness from about 20 Angstroms to about 80 Angstroms.
5. The method of claim 1 , wherein the differential thickness comprises a relatively thicker and a relatively thinner silicon oxide layer, and the relatively thinner silicon oxide layer has a thickness from about 10 Angstroms to about 50 Angstroms.
6. The method of claim 1 , wherein the differential thickness is from about 5 Angstroms to about 30 Angstroms.
7. A method for forming multiple width offset spacers adjacent respective MOSFET gate structures comprising the steps of:
providing a semiconductor substrate comprising at least two gate structures;
growing a silicon oxide layer having a respective differential thickness over the at least two gate structures;
forming a dielectric layer on the silicon oxide layer having an etching selectivity with respect to the silicon oxide layer;
forming offset spacers having a differential thickness comprising the dielectric layer and the silicon oxide layer adjacent either side of the at least two respective gate structures; and,
carrying out an ion implant process adjacent the offset spacers to form doped regions in the semiconductor substrate to form at least two MOSFET devices, wherein the differential thickness comprises a relatively thicker and a relatively thinner silicon oxide layer, the relatively thinner silicon oxide layer is formed in a MOSFET device having a relatively shorter gate length, and the relatively thicker silicon oxide layer is formed in a MOSFET device having a relatively longer gate length.
8. The method of claim 7 , wherein the step of growing a silicon oxide layer comprises a prior step of ion implanting at least one of the at least two different respective gate structures with an ion having a property selected from the group consisting of enhancing silicon oxide growth and suppressing silicon oxide growth.
9. The method of claim 7 , wherein the step of ion implanting comprises an ion selected from the group consisting of nitrogen and fluorine ions.
10. The method of claim 7 , wherein the differential thickness comprises a relatively thicker and a relatively thinner silicon oxide layer, and the relatively thicker silicon oxide layer has a thickness from about 20 Angstroms to about 80 Angstroms.
11. The method of claim 7 , wherein the differential thickness comprises a relatively thicker and a relatively thinner silicon oxide layer, and the relatively thinner silicon oxide layer has a thickness from about 10 Angstroms to about 50 Angstroms.