IP Library Granted Patent US 7,458,022
Granted Patent B2
US 7,458,022 · App. 10/889,614 · Granted Nov 25, 2008

Hardware/software partition for high performance structured data transformation

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,458,022
App. No.
10/889,614
Granted
Nov 25, 2008
Kind
B2
Abstract

An apparatus comprises a computer accessible medium encoded with a plurality of instructions which, when executed, compile a stylesheet into one or more data structures, and a hardware circuit coupled to receive the data structures and a document. The hardware circuit is configured to perform at least a portion of transforming the document as specified in the stylesheet using the data structures.

Claims (31)

1. An apparatus comprising:

a computer accessible medium encoded with a plurality of instructions which, when executed, compile a stylesheet into one or more data structures, wherein the data structures include one or more expression trees representing expressions in the stylesheet, wherein the expressions select nodes in a corresponding source document tree structure and further wherein each expression has a corresponding body that specifies a portion of an output document structure to be instantiated for each matching node; and

a hardware circuit coupled to receive the data structures and a document, wherein the hardware circuit is configured to perform at least a portion of transforming the document as specified in the stylesheet using the data structures and wherein the hardware circuit is configured to apply the expressions represented in the expression trees to the document to identify nodes in the document that satisfy the expressions, and further wherein the hardware circuit is configured to cause the transformed document to be stored in a memory device, wherein the plurality of instructions, when executed, assign serial numbers to each node identifier in the stylesheet, and wherein the data structures include one or more symbol tables stored in memory coupled with the hardware circuit that map the node identifiers to the serial numbers.

2. The apparatus as recited in claim 1 wherein the hardware circuit comprises a parser configured to parse the document, and wherein the parser is configured to detect the node identifiers in the document and is configured to convert the node identifiers to the serial numbers using the one or more symbol tables.

3. The apparatus as recited in claim 2 wherein, in response to detecting a first node identifier in the document that is not in the symbol tables, the parser is configured to assign a first serial number to the first node identifier.

4. The apparatus as recited in claim 3 wherein the parser is configured to store the first node identifier and the first serial number in a second one or more symbol tables generated by the parser.

5. The apparatus as recited in claim 1 further comprising a transformation engine configured to perform one or more actions on the nodes that satisfy a given expression as specified in the stylesheet.

6. The apparatus as recited in claim 5 wherein a portion of at least some expressions are evaluatable when applying the actions, and wherein the hardware circuit is configured to group nodes that satisfy a remainder of the expressions according to the portions.

7. The apparatus as recited in claim 1 wherein, if two or more expressions have a common portion, the two or more expressions share nodes in the expression tree that correspond to the common portion.

8. The apparatus as recited in claim 1 wherein the computer accessible medium further comprises a second plurality of instructions which, when executed, compile a schema into a second one or more data structures.

9. The apparatus as recited in claim 8 wherein the second data structures comprise a skeleton table that identifies valid document structure.

10. The apparatus as recited in claim 8 wherein the second data structures comprise one or more tables that identify default attribute value.

11. The apparatus as recited in claim 8 wherein the second data structures comprise one or more tables that identify required attributes of elements.

12. A method comprising:

compiling a stylesheet into one or more data structures, wherein the data structures include one or more expression trees representing expressions in the stylesheet;

receiving the data structures and a document into a hardware circuit;

the hardware circuit performing at least a portion of transforming the document as specified in the stylesheet using the data structures

the hardware circuit applying the expressions represented in the expression trees to the document to identify nodes in the document that satisfy the expressions;

the hardware circuit causing the transformed document to be stored in a memory device; and

assigning serial numbers to each node identifier in the stylesheet, and wherein the data structures include one or more symbol tables stored in memory coupled with the hardware circuit that map the node identifiers to the serial numbers.

13. The method as recited in claim 12 further comprising: the hardware circuit parsing the document to detect the node identifiers in the document; and the hardware circuit converting the node identifiers to the serial numbers using the one or more symbol tables.

14. The method as recited in claim 13 further comprising:

the hardware circuit detecting a first node identifier in the document that is not in the symbol tables;

the hardware circuit assigning a first serial number to the first node identifier; and

the hardware circuit storing the first node identifier and the first serial number in a second one or more symbol tables generated by the hardware circuit.

15. The method as recited in claim 12 further comprising the performing one or more actions on the nodes that satisfy a given expression as specified in the stylesheet.

16. The method as recited in claim 15 wherein a portion of at least some expressions are evaluatable when applying the actions, the method further comprising the hardware circuit grouping nodes that satisfy a remainder of the expressions according to the portions.

17. The method as recited in claim 12 further comprising compiling a schema into a second one or more data structures.

18. The method as recited in claim 17 wherein the second data structures comprise a skeleton table that identifies valid document structure.

19. The method as recited in claim 18 wherein the second data structures comprise one or more tables that identify default attribute value.

20. The method as recited in claim 18 wherein the second data structures comprise one or more tables that identify required attributes of elements.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2006
From: CONFORMATIVE SYSTEMS, INC.
To: INTEL CORPORATION
Reel/Frame 018141/0653 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2004
From: RAMARAO, KAREMPUDI V.
To: CONFORMATIVE SYSTEMS, INC.
Reel/Frame 015569/0804 →
Continuity (2)
Provisional Application 6051330600 · Oct 22, 2003
Related Publication 20050091589A1 · Apr 28, 2005