Semiconductor memory device of single-bit-line drive type
A semiconductor memory device includes a plurality of word lines, first and second bit lines, a plurality of memory cells which are connected to the first and second bit lines, a differential amplifier which is connected to one end of the first bit line and one end of the second bit line, a reference-current generating circuit which is connected to the other end of the second bit line and which generates a reference-current smaller than the cell current of the memory cells, and a dummy word line which is connected to the reference-current generating circuit, to activate the reference-current generating circuit in order to read data.
1. A semiconductor memory device comprising:
a plurality of word lines;
first and second bit lines;
a plurality of memory cells which are connected to the first and second bit lines, each memory cell having:
a first inverter having an input terminal and an output terminal;
a second inverter having an input terminal connected to the output terminal of the first inverter, and an output terminal connected to the input terminal of the first inverter;
a first transfer-gate transistor having a gate terminal connected to one of the word lines, and a first current path connected at one end to the first bit line and at the other end to at least the output terminal of the first inverter;
a second transfer-gate transistor having a gate terminal connected to one of the word lines, and a second current path connected at one end to the second bit line and at the other end to at least the output terminal of the second inverter;
a third transfer-gate transistor having a gate terminal connected to one of the word lines, and a third current path connected at one end to the first bit line; and
a reading-driver transistor having a gate terminal connected to at least the input terminal of the first inverter, and a fourth current path connected at one end to the other end of the third current path of the third transfer-gate transistor, and at the other end to a first power-supply terminal;
a differential amplifier which is connected to one end of the first bit line and one end of the second bit line;
a reference-current generating circuit which is connected to the other end of the second bit line and which generates a reference-current smaller than the cell current of the memory cells; and
a dummy word line which is connected to the reference-current generating circuit, to activate the reference-current generating circuit in order to read data.
2. The device according to claim 1 , wherein the plurality of memory cells are arranged, forming a plurality of sub-arrays, each sub-array consisting of a prescribed number of memory cells, the sub-arrays being arranged in rows and columns, forming one memory cell array.
3. The device according to claim 1 , wherein, of the first and second bit lines precharged to a predetermined power-supply voltage before data is read, the second bit line is connected to a bit-line clamping circuit which defines a lower limit of the potential of the second bit line in order to read data.
4. The device according to claim 1 , wherein the first and second inverters are CMOS (Complementary Metal Oxide Semiconductor) inverter, each comprising an N-channel MOS field-effect transistor and a P-channel MOS field-effect transistor, and the first, second and third transfer-gate transistors and the reading-driver transistor are N-channel MOS field-effect transistors.
5. The device according to claim 1 , wherein, in each of the memory cells, the first and second transfer-gate transistors and the first and second inverters constitute a data-holding unit, the third transfer-gate transistor and the reading-driver transistor constitute a data-reading unit, and at least one of the third transfer-gate transistor and reading-driver transistor has a lower threshold voltage than the first and second transfer-gate transistors and N-channel MOS field-effect transistors which constitute the first and second inverters.
6. The device according to claim 1 , wherein the reference-current generating circuit generates a reference current that is not more than half the cell current.
7. The device according to claim 1 , wherein the reference-current generating circuit comprise transistors forming two memory cells.
8. The device according to claim 1 , wherein the reference-current generating circuit has a first dummy cell and a second dummy cell; the first dummy cell includes a first dummy inverter having an input terminal and an output terminal, a second dummy inverter having an input terminal connected to the output terminal of the first dummy inverter and an output terminal connected to the input terminal of the first dummy inverter, a first dummy transfer-gate transistor having a gate terminal connected to the dummy word line and a first current path connected at one end to at least the output terminal of the first dummy inverter, a second dummy transfer-gate transistor having a gate terminal connected to the dummy word line and a second current path connected at one end to at least the output terminal of the second dummy inverter, a third dummy transfer-gate transistor having a gate terminal connected to the dummy word line, and a first dummy reading-driver transistor having a gate terminal connected to at least the input terminal of the first dummy inverter and a fourth current path connected, at one end, to the other end of a third current path of the third dummy transfer-gate transistor and, at the other end, to the second bit line; and the second dummy cell includes a third dummy inverter having an input terminal and an output terminal, a fourth dummy inverter having an input terminal connected to the output terminal of the third dummy inverter and an output terminal connected to the input terminal of the third dummy inverter, a fourth dummy transfer-gate transistor having a gate terminal connected to the dummy word line and a fifth current path connected at one end to at least the output terminal of the third dummy inverter, a fifth dummy transfer-gate transistor having a gate terminal connected to the dummy word line and a sixth current path connected at one end to at least the output terminal of the fourth dummy inverter, a sixth dummy transfer-gate transistor having a gate terminal connected to the dummy word line, and a second dummy reading-driver transistor having a gate terminal connected to at least the input terminal of the third dummy inverter and an eighth current path connected, at one end, to the other end of a seventh current path of the sixth dummy transfer-gate transistor and, at the other end, to the first power-supply terminal.
9. The device according to claim 8 , wherein, in the reference-current generating circuit, the second dummy inverter and the fourth dummy inverter are connected at input terminal to the first power-supply terminal, the first and second dummy cells have internal nodes fixed at a reference potential, and the N-channel MOS field-effect transistors constituting the first dummy inverter are connected at source terminal to the second bit line.
10. The device according to claim 8 , wherein, in the reference-current generating circuit, the second dummy inverter and the fourth dummy inverter are connected at input terminal to the first power-supply terminal, the first and second dummy cells have internal nodes fixed at a reference potential, and the N-channel MOS field-effect transistors constituting the first dummy inverter are connected at source terminal to the first power-supply terminal.
11. The device according to claim 8 , wherein, in the reference-current generating circuit, the first dummy inverter and the third dummy inverter are connected at input terminal to a second power-supply terminal, the first and second dummy cells have internal nodes fixed to a power-supply voltage, and the N-channel MOS field-effect transistors constituting the first dummy inverter are connected at source terminal to the second bit line.
12. The device according to claim 8 , wherein, in the reference-current generating circuit, the first dummy inverter and the third dummy inverter are connected at input terminal to a second power-supply terminal, the first and second dummy cells have internal nodes fixed at a power-supply voltage, and the N-channel MOS field-effect transistors constituting the first dummy inverter are connected at source terminal to the first power-supply terminal.
13. The device according to claim 8 , wherein, in the reference-current generating circuit, the second current path of the second dummy transfer-gate transistor and the sixth current path of the fifth dummy transfer-gate transistor are connected at the other end to each other.
14. The device according to claim 8 , wherein, in the reference-current generating circuit, the third current path of the third dummy transfer-gate transistor and the seventh current path of the sixth dummy transfer-gate transistor are connected at one end to each other.