Methods of fabricating alignment key structures in semiconductor devices including protected electrode structures
An integrated circuit device includes a storage cell including an upper electrode and a lower electrode on a substrate, and a conductive hard mask pattern directly on the upper electrode of the storage cell opposite the lower electrode. The upper electrode is formed of a metal softer than the conductive hard mask pattern. The device further includes an interlayer on the substrate having an alignment key recess therein. The alignment key recess extends towards the substrate beyond a depth of the upper electrode. An alignment key pattern may extend towards the substrate beyond the depth of the upper electrode on opposing sidewalls and on a surface therebetween of the alignment key recess. The alignment key pattern may have a distinct step difference between portions thereof on the opposing sidewalls and portions thereof on the surface therebetween. Related methods are also discussed.
1. A method of forming an integrated circuit device, the method comprising:
forming a conductive hard mask pattern directly on an upper electrode of a storage cell on a substrate, the upper electrode comprising a metal softer than the conductive hard mask pattern; and
forming an interlayer on the substrate;
recessing a portion of the interlayer beyond a depth of the upper electrode to form an alignment key recess therein extending towards the substrate beyond the depth of the upper electrode; and
forming a conductive layer on opposing sidewalls and a surface therebetween of the alignment key recess to define an alignment key pattern extending towards the substrate beyond the depth of the upper electrode and having a distinct step difference between portions thereof on the opposing sidewalls and portions thereof on the surface therebetween.
2. The method of claim 1 , wherein an angle between the portions of the alignment key pattern on the opposing sidewalls and the portions on the surface therebetween comprises about 90 degrees.
3. The method of claim 1 , further comprising:
recessing the interlayer in a peripheral region of the substrate to define a peripheral contact hole therein; and
forming the conductive layer in the contact hole to form a contact pattern in the peripheral region.
4. The method of claim 1 , wherein the conductive hard mask pattern comprises a material having a high etch selectivity relative to the interlayer, and wherein recessing a portion of the interlayer comprises:
selectively etching the portion of the interlayer using the conductive hard mask pattern as an etch stop layer.
5. The method of claim 1 , further comprising:
forming the interlayer on the conductive hard mask pattern;
forming a cell contact hole in the interlayer exposing at least a portion of the conductive hard mask pattern;
forming an upper electrode contact pattern in the cell contact hole electrically connected to the conductive hard mask pattern opposite the upper electrode; and
forming an interconnection layer on the interlayer and electrically connected to the upper electrode contact pattern.
6. The method of claim 5 , wherein forming the cell contact hole comprises forming the cell contact hole in a same step as recessing the interlayer to form the alignment key recess, and wherein forming the conductive layer comprises forming the conductive layer in the alignment key recess and in the cell contact hole to define the alignment key pattern and the upper electrode contact pattern in a same step.
7. The method of claim 1 , further comprising:
forming an interconnection layer directly on the conductive hard mask pattern opposite the upper electrode.
8. The method of claim 1 , wherein the conductive hard mask pattern comprises a low-resistance metal layer, and wherein the interlayer comprises an insulating layer.
9. The method of claim 1 , wherein the upper electrode comprises titanium (Ti) and/or titanium nitride (TiN), and wherein the conductive hard mask pattern comprises iridium (Ir) and/or iridium oxide (IrO).
10. The method of claim 1 , wherein the storage cell comprises a phase-changeable memory cell including the upper and lower electrodes and a phase-changeable material layer therebetween.