Writing a circuit design pattern with shaped particle beam flashes
A shaped particle beam writing strategy can be used to write a pattern with a particle beam onto a substrate. The pattern comprises a circuit design that is fractured into a plurality of arbitrary polygons. The writing strategy comprises transforming and fracturing the arbitrary polygons into a plurality of restricted polygons, each restricted polygon being represented by a location coordinate, at least two dimension coordinates, and at least one external edge indicator. Thereafter, the restricted polygons are tiled into a set of tiles comprising interior tiles and external edge tiles. Flash data is assigned for each tile such that the interior tiles are assigned a first flash area and the external edge tiles are assigned a second flash area that is smaller than the first flash area. The flash data is arranged in a selected order to write the pattern with a modulated particle beam, such as an electron beam, on a substrate.
1. A shaped particle beam writing strategy for writing a circuit design pattern with a particle beam onto a substrate, the circuit design pattern comprising a plurality of polygons, and the writing strategy comprising:
(a) tiling the polygons into a set of tiles comprising interior tiles and external edge tiles;
(b) assigning a flash area for each tile such that the interior tiles are assigned a first flash area and the external edge tiles are assigned a second flash area that is smaller than the first flash area; and
(c) arranging the flashes in a selected order to write the circuit design pattern with a particle beam onto a substrate.
2. A writing strategy according to claim 1 wherein the second flash area is less than about ¾ the first flash area.
3. A writing strategy according to claim 1 wherein the second flash area is less than or equal to about λ 2 , where λ is a characteristic dimension of the electron beam.
4. A writing strategy according to claim 3 wherein the first flash area is less than or equal to about 2λ 2 .
5. A writing strategy according to claim 3 wherein any dimension of the first or second flash area is less than or equal to about 3/2λ.
6. A writing strategy according to claim 3 wherein λ is from 50 nm to about 200 nm.
7. A writing strategy according to claim 3 wherein λ is about 128 nm.
8. A writing strategy according to claim 1 wherein the shaped particle beam comprises a shaped electron beam.
9. A writing strategy according to claim 1 wherein the selected order of flashes is a raster, vector, or hybrid raster-vector scan.
10. A writing strategy according to claim 1 comprising the initial steps of:
(1) reading a circuit design pattern comprising a set of geometric primitives composed of arbitrary polygons; and
(2) fracturing the arbitrary polygons into a plurality of restricted polygons, wherein each restricted polygon is represented by a location coordinate, at least two dimension coordinates, and at least one external edge indicator.
11. A writing strategy for writing a circuit design pattern with an electron beam onto a substrate, the writing strategy comprising:
(a) reading a circuit design pattern comprising a set of geometric primitives composed of arbitrary polygons;
(b) fracturing the arbitrary polygons into a plurality of restricted polygons, each restricted polygon being represented by a location coordinate, at least two dimension coordinates, and at least one external edge indicator;
(c) tiling the restricted polygons into a set of tiles comprising interior tiles and external edge tiles;
(d) assigning an electron beam flash area to each tile, the electron beam flash comprising a first flash area for an interior tile and a second flash area for an external edge tile, the second flash area being smaller than the first flash area;
(e) arranging the electron beam flashes in a selected order; and
(f) moving an electron beam across a substrate and modulating the electron beam to flash the beam in the selected order to write the circuit design pattern onto the substrate.
12. A writing strategy according to claim 11 wherein the second flash area is less than about ¾ the first flash area.
13. A writing strategy according to claim 11 wherein the second flash area is less than or equal to about λ 2 , where λ is a characteristic dimension of the electron beam.
14. A writing strategy according to claim 13 wherein the first flash area is less than or equal to about 2λ 2 .
15. A writing strategy according to claim 13 wherein any dimension of the first or second flash area is less than or equal to about 3/2λ.
16. A writing strategy according to claim 13 wherein λ is from 50 to about 200 nm.