IP Library Granted Patent US 7,476,977
Granted Patent B2
US 7,476,977 · App. 11/056,169 · Granted Jan 13, 2009

Semiconductor chip mounting substrate, a method of producing the same, and a method of mounting a semiconductor chip

Assignee: Hitachi, Ltd.
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Quick Facts
Patent No.
US 7,476,977
App. No.
11/056,169
Granted
Jan 13, 2009
Kind
B2
Abstract

A chip mounting substrate for bonding a semiconductor chip to a substrate, comprises a solder layer on the substrate, the solder layer being connectable to a semiconductor chip, wherein the solder layer comprises a layer including δ-phase crystal grains of an Au—Sn alloy at a surface of the solder layer. The solder layer comprising a layer including δ-phase crystal grains of an Au—Sn alloy is formed at a surface of the solder layer. On mounting a semiconductor chip on the substrate, the substrate and the solder layer are heated and an image of the solder layer is shot to perform an image evaluation to detect the timing of mounting the semiconductor chip on the solder layer of the substrate and a position of the chip.

Claims (20)

1. A chip mounting substrate comprising;

a substrate; and

a solder layer on the substrate, the solder layer being connectable to a semiconductor chip,

wherein the solder layer comprises a layer including δ-phase crystal grains of an Au—Sn alloy at an outer surface of the solder layer; and

wherein a part of the solder layer other than the layer comprises two layers vertically arranged to a surface of the substrate, wherein the two layers comprise different compositions in Au and Sn from each other.

2. A chip mounting substrate comprising:

a substrate; and

a solder layer on the substrate, the solder layer being connectable to a semiconductor chip,

wherein the solder layer comprises at an outer surface of the solder layer a marker layer comprising a composition of an Au—Sn alloy in which, when the solder layer melts, crystal grains are precipitated to provide a visual indication that the solder layer melts, and

wherein a part of the solder layer other than the layer, comprises two layers vertically arranged to a surface of the substrate, wherein the two layers comprise different compositions in Au and Sn from each other.

3. A chip mounting substrate comprising;

a substrate; and

a solder layer on the substrate, the solder layer being connectable to a semiconductor chip,

wherein the solder layer comprises a layer including δ-phase crystal grains of an Au—Sn alloy at an outer surface of the solder layer, and

wherein the solder layer comprises first and second layers each comprising δ-phase crystal grains of an Au—Sn alloy and a third layer comprising a eutectic composition defined by a eutectic point of the Au—Sn alloy, and wherein the third layer is sandwiched between the first and second layers.

4. A chip mounting substrate comprising:

a substrate; and

a solder layer on the substrate, the solder layer being connectable to a semiconductor chip,

wherein the solder layer comprises at an outer surface of the solder layer a marker layer comprising a composition of an Au—Sn alloy in which, when the solder layer melts, crystal grains are precipitated to provide a visual indication that the solder layer melts, and

wherein the solder layer comprises first and second layers each comprising δ-phase crystal grains of an Au—Sn alloy and a third layer comprising a eutectic composition defined by a eutectic point of the Au—Sn alloy, and wherein the third layer is sandwiched between the first and second layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2005
From: FUJINAGA, TAKERU; HIROSE, KAZUHIRO; TAKEMORI, HIDEAKI; KOIZUMI, TOSHIAKI
To: HITACHI, LTD.
Reel/Frame 016288/0636 →
Priority Claims (1)
JP 2004-093999 · Mar 29, 2004 · national
Continuity (1)
Related Publication 20050212140A1 · Sep 29, 2005