IP Library › Granted Patent US 7,479,769
Granted Patent B2
US 7,479,769 · App. 10/570,245 · Granted Jan 20, 2009

Power delivery system having cascaded buck stages

Assignee: NXP B.V.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,479,769
App. No.
10/570,245
Granted
Jan 20, 2009
Kind
B2
Abstract

A power delivery system for a microprocessor or other ASIC. The power delivery system includes a plurality of cascaded buck stages connected in series, wherein a last buck stage in the plurality of cascaded buck stages provides an output voltage V o in response to an input voltage V in applied to a first buck stage of the plurality of cascaded stages. A duty cycle control regulates a duty cycle of each buck stage to maintain the output voltage V o . The duty cycle control sets the duty cycle of the first buck stage of the plurality of cascaded buck stages to 1 if an input-to-output voltage ratio (V in /V o ) is lower than a threshold input-to-output voltage ratio R T .

Claims (27)

1. A power delivery system, comprising:

a plurality of cascaded buck stages connected in series, wherein a last buck stage in the plurality of cascaded buck stages provides an output voltage V o in response to an input voltage V in applied to a first buck stage of the plurality of cascaded stages; and

a duty cycle control for controlling a duty cycle of each buck stage to maintain the output voltage V o , wherein the duty cycle control sets the duty cycle of the first buck stage of the plurality of cascaded buck stages to 1 if an input-to-output voltage ratio (V in /V o ) is lower than a threshold input-to-output voltage ratio R T .

2. The power delivery system of claim 1 , wherein each of the plurality of cascaded buck stages comprises one or more interleaved synchronous buck channels arranged in parallel.

3. The power delivery system of claim 2 , wherein each buck channel includes first and second switches SW 1 , SW 2 , and wherein the first switch SW 1 of the first buck stage is always on and the second switch SW 2 is always off when the duty cycle of the first buck stage is set to 1 by the duty cycle control.

4. The power delivery system of claim 1 , wherein the first buck stage operates as an input filter when the duty cycle of the first buck stage is set to 1 by the duty cycle control.

5. The power delivery system of claim 1 , wherein the duty cycle control sets the duty cycle of the first buck stage to a value less than 1 if the input-to-output voltage ratio (V in /V o ) is higher than the threshold input-to-output voltage ratio R T .

6. The power delivery system of claim 1 , wherein two cascaded buck stages are connected in series.

7. The power delivery system of claim 1 , wherein the input voltage V in comprises a bus voltage of about 12 V or a battery voltage of 6-24 V, and the output voltage V o is a voltage of 0.x-1.x V.

8. The power delivery system of claim 1 , wherein the system is operated at a switching frequency of at least one MHz.

9. A method for power delivery, comprising:

connecting a plurality of cascaded buck stages in series, wherein a last buck stage in the plurality of cascaded buck stages provides an output voltage V o in response to an input voltage V in applied to a first buck stage of the plurality of cascaded stages; and

controlling a duty cycle of each buck stage to maintain the output voltage V o , wherein the duty cycle of the first buck stage of the plurality of cascaded buck stages is set to 1 if an input-to-output voltage ratio (V in /V o ) is lower than a threshold input-to-output voltage ratio R T .

10. The power delivery method of claim 9 , wherein each of the plurality of cascaded buck stages comprises one or more interleaved synchronous buck channels arranged in parallel.

11. The power delivery method of claim 10 , wherein each buck channel includes first and second switches SW 1 , SW 2 , and wherein the first switch SW 1 of the first buck stage is always on and the second switch SW 2 is always off when the duty cycle of the first buck stage is set to 1.

12. The power delivery method of claim 9 , wherein the first buck stage operates as an input filter when the duty cycle of the first buck stage is set to 1.

13. The power delivery method of claim 9 , wherein the duty cycle of the first buck stage is set to a value less than 1 if the input-to-output voltage ratio (V in /V o ) is higher than the threshold input-to-output voltage ratio R T .

14. The power delivery method of claim 9 , wherein two cascaded buck stages are connected in series.

15. The power delivery method of claim 9 , wherein the input voltage V in comprises a bus voltage of about 12 V or a battery voltage of 6-24 V, and the output voltage V o is a voltage of 0.x-1.x V.

16. The power delivery method of claim 9 , further comprising:

operating the system at a switching frequency of at least one MHz.

17. A quasi-single-stage power delivery system, comprising:

first and second cascaded buck stages connected in series, wherein the second buck stage provides an output voltage V o in response to an input voltage V in applied to the first buck stage; and

a duty cycle control for controlling duty cycles of the first and second buck stages to maintain the output voltage V o , wherein the duty cycle of the first buck stage is set to 1 if an input-to-output voltage ratio (V in /V o ) is lower than a threshold input-to-output voltage ratio R T , and wherein the duty cycle of the first buck stage is set to a value less than 1 if the input-to-output voltage ratio (V in /V o ) is higher than the threshold input-to-output voltage ratio R T .

18. The quasi-single-stage power delivery system of claim 17 , wherein the first and second buck stages each comprise one or more interleaved synchronous buck channels arranged in parallel.

19. The quasi-single-stage power delivery system of claim 18 , wherein each buck channel includes first and second switches SW 1 , SW 2 , and wherein the first switch SW 1 of the first buck stage is always on and the second switch SW 2 of the first buck stage is always off when the duty cycle of the first buck stage is set to 1 by the duty cycle control.

20. The quasi-single-stage power delivery system of claim 17 , wherein the first buck stage operates as an input filter when the duty cycle of the first buck stage is set to 1 by the duty cycle control.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2013
From: NXP B.V.
To: COMMONWEALTH RESEARCH GROUP, LLC
Reel/Frame 031196/0007 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: NXP B.V.
To: COMMONWEALTH RESEARCH GROUP, LLC
Reel/Frame 025105/0183 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2006
From: XU, PENG
To: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
Reel/Frame 017640/0402 →
Continuity (2)
Provisional Application 6049885900 · Aug 29, 2003
Related Publication 20070001653A1 · Jan 4, 2007