Customizable ASIC with substantially non-customizable portion that supplies pixel data to a mask-programmable portion in multiple color space formats
An integrated circuit has a substantially non-customizable hardware portion and a mask-programmable logic portion. An image processing function common to many different makes and models of a type of electronic consumer device (for example, an image display device) is performed by the substantially non-customizable hardware portion. The substantially non-customizable hardware portion also outputs pixel data in both a first color space format and a second color space format. The mask-programmble logic portion can be mask-programmed for an individual manufacturer of electronic consumer devices such that the mask-programmable logic portion performs an additional special function specific to the electronic consumer devices of the individual manufacturer. Certain functions are better or more easily performed on pixel data in one color space format than another. Pixel data is therefore supplied to the mask-programmable hardware portion in multiple different color space formats, or in a selectable one of multiple different color space formats.
1. An integrated circuit, comprising:
a substantially non-customizable hardware portion; and
a mask-programmable logic portion that is coupled to receive first pixel data from the substantially non-customizable hardware portion in a first color space format and to receive second pixel data from the substantially non-customizable hardware portion in a second color space format.
2. The integrated circuit of claim 1 , wherein the substantially non-customizable hardware portion includes a color space conversion circuit.
3. The integrated circuit of claim 1 , wherein the substantially non-customizable hardware portion performs a video processing function, and wherein the mask-programmable logic portion is mask-programmed to perform an enhancement function.
4. The integrated circuit of claim 1 , wherein the mask-programmable logic portion is coupled to receive the first pixel data from the substantially non-customizable hardware portion in the first color space format via a first parallel bus, the mask-programmable logic portion further receiving a signal from the substantially non-customizable hardware portion that is indicative of whether valid pixel data is present on the first parallel bus.
5. An integrated circuit, comprising:
a substantially non-customizable hardware portion; and
a mask-programmable logic portion that is coupled to receive first pixel data from the substantially non-customizable hardware portion in a first color space format and to receive second pixel data from the substantially non-customizable hardware portion in a second color space format, wherein the mask-programmable logic portion is coupled to receive the first pixel data from the substantially non-customizable hardware portion in the first color space format via a first parallel bus, wherein the mask-programmable logic portion further receives a signal from the substantially non-customizable hardware portion that is indicative of whether valid pixel data is present on the first parallel bus, and wherein the mask-programmable logic portion is coupled to output third pixel data in the first color space format to the substantially non-customizable hardware portion via a second parallel bus, the mask-programmable logic portion outputting a signal to the substantially non-customizable hardware portion that is indicative of whether valid pixel data is present on the second parallel bus.
6. The integrated circuit of claim 1 , wherein the mask-programmable logic portion is mask-programmed to perform an enhancement function on the first pixel data, the enhancement function being from the group consisting of: white level enhancement, black level enhancement, color histogram extension, flesh-tone enhancement, horizontal DLTI, peaking filtering, display control and OCTI (Digital Chrominance Transient Improvement), and wherein the first color space format is a YCbCr color space.
7. The integrated circuit of claim 1 , wherein the mask-programmable logic portion is mask-programmed to perform an enhancement function on the first pixel data, the enhancement function being from the group consisting of:
gamma correction and dithering, wherein the first color space format is an RGB color space.
8. The integrated circuit of claim 1 , wherein the substantially non-customizable hardware portion occupies substantially more integrated circuit die area than the mask-programmable logic portion occupies.
9. The integrated circuit of claim 1 , wherein the integrated circuit is disposed in a video display device.
10. The integrated circuit of claim 1 , wherein the substantially non-customizable hardware portion includes a configuration register, and wherein the substantially non-customizable hardware portion is configurable by writing configuration information into the configuration register.
11. The integrated circuit of claim 1 , wherein the substantially non-customizable hardware portion is realized at least in part of standard cells.
12. An integrated circuit, comprising:
a substantially non-customizable hardware portion; and
a mask-programmable logic portion that is coupled to receive pixel data from the substantially non-customizable hardware portion in a selectable one of either a first color space format or a second color space format.
13. The integrated circuit of claim 1 , further comprising:
interface circuitry for interfacing an external FPGA to the integrated circuit.
14. The integrated circuit of claim 13 , wherein the integrated circuit comprises:
a multiplexer selectable to supply either the pixel data in the first color space format to the mask-programmable logic portion or to supply the pixel data in the second color space format to the mask-programmable logic portion.
15. The integrated circuit of claim 14 , wherein the multiplexer is part of the mask-programmable logic portion.
16. The integrated circuit of claim 14 , wherein the multiplexer is part of the substantially non-customizable hardware portion.
17. The integrated circuit of claim 13 , further comprising:
interface circuitry for interfacing an external FPGA to the integrated circuit.
18. A method, comprising:
performing a video processing function in a substantially non-customizable hardware portion of an integrated circuit, the substantially non-customizable hardware portion outputting pixel data in a first color space format and pixel data in a second color space format;
receiving the pixel data in the first color space format onto a mask-programmable logic portion of the integrated circuit; and
receiving the pixel data in the second color space format onto the mask-programmable logic portion of the integrated circuit.
19. The method of claim 18 , wherein the first color space format is a YCbCr color space format, and wherein the second color space format is an RGB color space format.
20. An integrated circuit, comprising:
a substantially non-customizable hardware portion that performs a video processing function; and
means for receiving pixel data from the substantially non-customizable hardware portion in a first color space format and for receiving pixel data from the substantially non-customizable hardware portion in a second color space format, wherein the means is mask-programmable.
21. The integrated circuit of claim 20 , wherein the means includes an amount of mask-programmable logic, and wherein the means is mask-programmed to perform a video enhancement function.
22. The integrated circuit of claim 21 , wherein the substantially non-customizable hardware portion includes a color space conversion circuit.