Silicon carbide semiconductor device
A silicon carbide semiconductor device is provided with a semiconductor substrate ( 20 ) of silicon carbide of a first conductivity type, a hetero semiconductor region ( 60 ) forming a hetero-junction with the semiconductor substrate ( 20 ), an insulated gate including a gate electrode ( 40 ) and a gate insulator layer ( 30 ) formed on the semiconductor substrate ( 20 ) and adjoining to the hetero semiconductor region ( 60 ), a source electrode ( 80 ) electrically connected to the hetero semiconductor region ( 60 ) and a drain electrode ( 90 ) electrically connected to the semiconductor substrate ( 20 ).
1. A semiconductor device comprising:
a drain region including a first semiconductor of a first conduction type;
a source region including a second semiconductor having a band gap different from that of the first semiconductor, the source region forming hetero junction with the drain region;
a gate insulator in contact with the hetero junction; and
a gate conducting region having the gate insulator interposed between the gate conducting region and the hetero junction.
2. The semiconductor device of claim 1 , wherein the first semiconductor includes a highly doped silicon carbide semiconductor and a lowly doped silicon carbide epitaxial region being epitaxial with the highly doped silicon carbide semiconductor, and the epitaxial region forms the hetero junction with the source region.
3. The semiconductor device of claim 2 , wherein the epitaxial region includes a second conduction type region in contact with the gate insulator.
4. The semiconductor device of claim 2 , wherein the epitaxial region includes a trench filled with the source region.
5. The semiconductor device of claim 2 , wherein the epitaxial region includes a second conduction type region in contact with the source region.
6. The semiconductor device of claim 2 , further comprising:
a trench penetrating the source region to reach the epitaxial region, the trench being filled with the gate insulator in contact with the epitaxial region and the gate conduction region having the gate insulator interposed between the gate conduction region and the epitaxial region.
7. The semiconductor device of claim 2 , wherein the epitaxial region includes a second epitaxial region having a conduction type identical to that of the epitaxial region and an impurity concentration different from that of the epitaxial region, and the second epitaxial region is in contact with the source region.
8. The semiconductor device of claim 1 , wherein the source region includes a second source region having an impurity concentration different from that of the source region.
9. The semiconductor device of claim 1 , wherein the source region includes one selected from the group of crystalline silicon, amorphous silicon and a polycrystalline silicon.