Method for achieving uniform etch depth using ion implantation and a timed etch
A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.
1. A method of performing a timed etch of an isolation material to a precise depth, the isolation material being formed between ridges of a patterned layer, the method comprising:
performing an ion implantation of the isolation material and the patterned layer, thereby damaging the isolation material and the patterned layer to the precise depth;
performing the timed etch to provide a vertical dimension of the isolation material in relation to the patterned layer, which is unaffected by the timed etch; and
performing an annealing to repair the patterned layer,
wherein damaged isolation material etches faster than undamaged isolation material, thereby ensuring that the vertical dimension of the isolation material in relation to the patterned layer is substantially equal to the precise depth.
2. The method of claim 1 , wherein the isolation material is a dielectric.
3. The method of claim 1 , wherein the isolation material is silicon dioxide.
4. The method of claim 1 , wherein the isolation material is a field oxide.
5. The method of claim 1 , wherein the patterned layer forms a transistor with a segmented channel.
6. The method of claim 1 , wherein the patterned layer forms an inverted T-channel field-effect transistor (ITFET).
7. The method of claim 1 , wherein the patterned layer forms a capacitor.
8. The method of claim 1 , wherein the ion implantation includes argon.
9. The method of claim 1 , wherein the ion implantation includes germanium.