IP Library › Granted Patent US 7,495,736
Granted Patent B2
US 7,495,736 · App. 11/214,875 · Granted Feb 24, 2009

Pixel array with flexible circuit layout having respective scan and data line profiles with predetermined wave construction so as to evenly distribute any strain on the respective scan and data lines to withstand stress and be flexible

Assignee: Industrial Technology Research Instituti
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Quick Facts
Patent No.
US 7,495,736
App. No.
11/214,875
Granted
Feb 24, 2009
Kind
B2
Abstract

A pixel array with flexible circuit layout is disclosed, which comprises: a substrate, having a first surface; a plurality of scan lines; and a plurality of data lines; wherein the plural scan lines are disposed on the first surface while each has a profile defined by a non-linear first function, and the plural data lines are disposed on the first surface while each has a profile defined by a non-linear second function. When the pixel array is adapted for a flexible display and the display is being bended, the flexible circuit layout of the pixel array of the invention can effectively reduce the risk of the snapping of the conductive wires used in the pixel array so that the flexibility and reliability of the flexible display are enhanced.

Claims (19)

1. A pixel array with flexible circuit layout, being adapted for a flexible display, comprising:

a substrate, having a first surface;

a plurality of scan lines, disposed on the first surface while each has a profile defined by a non-linear first function; and

a plurality of data lines, disposed on the first surface while each has a profile defined by a non-linear second function,

wherein said non-linear first and second profile functions of said respective scan and data lines are of a predetermined wave construction so as to evenly distribute any strain on said respective scan and data lines to thereby withstand stress and be flexible.

2. The pixel array of claim 1 , wherein the profile of the first function is a sine wave.

3. The pixel array of claim 1 , wherein the profile of the first function is a square wave.

4. The pixel array of claim 1 , wherein the profile of the first function is a triangle wave.

5. The pixel array of claim 1 , wherein the profile of the second function is a sine wave.

6. The pixel array of claim 1 , wherein the profile of the second function is a square wave.

7. The pixel array of claim 1 , wherein the profile of the second function is a triangle wave.

8. The pixel array of claim 1 , wherein the substrate is made of a material selected from the group consisting of glass, plastic, metal, flexible materials.

9. The pixel array of claim 1 , wherein the plural scan lines are made of a metal.

10. The pixel array of claim 1 , wherein the plural data lines are made of a metal.

11. The pixel array of claim 1 , wherein the arrangement of the plural scan lines and the plural data lines forms an interlacing pattern.

12. The pixel array of claim 11 , wherein a pixel is defined by any two neighboring scan lines and any two neighboring data lines of the interlacing pattern.

13. The pixel array of claim 12 , wherein each pixel defined in the interlacing pattern further comprises a thin film transistor connected respectively to the corresponding scan lines and data lines.

14. The pixel array of claim 13 , wherein the thin film transistor is a PMOS transistor.

15. The pixel array of claim 13 , wherein the thin film transistor is a NMOS transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2005
From: CHEN, BO-CHU; TSENG, HUAI-YUAN; YEH, YUNG-HUI; LIN, CHING-CHIEH
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 016944/0633 →
Priority Claims (1)
TW 94124447 A · Jul 20, 2005 · national
Continuity (1)
Related Publication 20070019143A1 · Jan 25, 2007