Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line
View Patent ↗An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.
1. An SRAM memory array comprising:
a plurality of memory cells, each of said plurality of memory cells further comprising:
a device, each of said plurality of memory cells having seven of said device;
a first storage node;
a second storage node; and
a first local bit line;
said first storage node and said second storage node store true and complement of data and are constructed with six of said device forming a cross-coupled flip-flop cell, one of said device being configured as a first read-pass device, said second storage node is connected to said first read-pass device, said first read-pass device passes the state of said second storage node to said first local bit line effectuating single ended sensing, said first read-pass device gate is connected to a first read word line, wherein said device is a transistor, nFET, or pFET;
a first global bit line, one of said device configured as a first read-head nFET for selectively discharging to ground a previously precharged said first global bit line effectuating passing by way of said first read-head nFET the inverse of a first signal on said first local bit line to said first global bit line, said first local bit line is connected to 1 or more other said plurality of memory cells, said first global bit line passing said first signal to a first sense amplifier.
2. The SRAM memory array in accordance with claim 1 , said SRAM memory array further comprising:
a second local bit line, one of said device being configured as a second read-pass device, said first storage node is connected to said second read-pass device, said second read-pass device passes the state of said first storage node to said second local bit line effectuating single ended sensing, said second read-pass device gate is connected to a second read word line.
3. The SRAM memory array in accordance with claim 2 , said SRAM memory array further comprising:
a second global bit line, one of said device configured as a second read-head nFET for selectively discharging to ground a previously precharged said second global bit line effectuating passing by way of said second read-head nFET the inverse of a second signal on said second local bit line to said second global bit line, said second local bit line is connected to at most thirty-two other said plurality of memory cells, said second global bit line passing said second signal to a second sense amplifier.
4. The SRAM memory array in accordance with claim 3 , wherein said SRAM memory array is configured as a three port array where two separate reads and one separate write, on the same said plurality of memory cells or on different said plurality of memory cells, can be performed in a single cycle.