Structure of image sensor module and method for manufacturing of wafer level package

1. A process of wafer level package, comprising the steps of:

forming a first photo resist pattern on metal pads of a plurality of dies on a wafer to cover said metal pads;

forming a first dielectric layer on said first photo resist pattern and said

plurality of dies; curing said first dielectric layer;

removing said first photo resist pattern;

sawing said plurality of dies on said wafer to form individual dies;

selecting good said dies and attaching said good dies to an isolating base;

curing said isolating base;

forming a material layer on said isolating base to fill in a space among said plurality of dies on said isolating base;

curing said material layer;

forming a second dielectric layer on said material layer and said metal pads;

etching a partial region of said second dielectric layer on said metal pads to form first openings on said metal pads;

curing said second dielectric layer; forming a contact conductive layer on said first openings to electrically couple with said metal pads, respectively;

forming a second photo resist layer on said second dielectric layer and said contact conductive layer;

removing a partial region of said second photo resist layer to form a second photo resist pattern and expose said contact conductive layer to form second openings;

forming conductive lines on said second photo resist pattern and said second openings being coupled with said contact conductive layer, respectively;

removing remaining said second photo resist layer;

forming an isolation layer on said conductive lines and said second dielectric layer;

removing a partial region of said isolation layer on said conductive lines to form third openings;

curing said isolation layer; and

welding solder balls on said third openings.

2. The process in claim 1 , further comprising a step of sawing said isolating base to isolate said plurality of dies after the step of said welding solder balls.

3. The process in claim 1 , further comprising a step of back lapping said wafer to get a thickness of said wafer around 100-300 μm after the step of said removing first photo resist pattern.

4. The process in claim 1 , further comprising a step of forming an epoxy layer on back surface of said isolating base.

5. The process in claim 1 , wherein said plurality of dies comprise at least two types of dies.

6. The process in claim 1 , wherein material of said first dielectric layer is SiO 2 by spin coating.

7. The process in claim 1 , wherein material of said isolating base is glass, silicon, ceramic or quartz crystal.

8. The process in claim 1 , wherein material of said material layer is silicon rubber, epoxy, BCB, BT, polyimide (PI) or SINR(Siloxane polymer).

9. The process in claim 1 , wherein material of said second dielectric layer is silicon rubber, epoxy, SINR(Siloxane polymer), BCB or polyimide (PI).

10. The process in claim 1 , further comprising a step of forming a filtering film on said first dielectric layer, said filtering film is an IR filtering layer.

11. The process in claim 1 , wherein material of said contact conductive layer is selected from Ti, Cu and the combination thereof.

12. The process in claim 1 , wherein material of said isolation layer is selected from epoxy, resin and the combination thereof.

13. The process in claim 1 , wherein material of said conductive lines is selected from Ni, Cu, Au and the combination thereof.

14. The process in claim 1 , wherein said step of welding said solder balls comprises placing said solder balls on said third openings by a screen printing method and joining said solder balls together with surfaces of said conductive lines by an IR reflow method.

15. A process of wafer level package, comprising the steps of:

forming a first dielectric layer on a plurality of dies on a wafer by using a first photo resist pattern;

sawing said plurality of dies on said wafer to form individual dies;

selecting good said dies and attaching said good dies to a isolating base;

forming a material layer on said isolating base to fill in a space among said plurality of dies;

forming a second dielectric layer on said material layer;

etching a partial region of said second dielectric layer to form first openings to expose metal pads on said dies;

forming a contact conductive layer on said first openings to electrically couple with said metal pads, respectively;

forming a second photo resist pattern to expose said contact conductive layer to form second openings;

forming conductive lines on said second photo resist pattern and said second openings being coupled with said contact conductive layer, respectively;

removing remaining said second photo resist pattern;

forming an isolation layer on said conductive lines and said second dielectric layer;

removing a partial region of said isolation layer on said conductive lines to form third openings; and

welding solder balls on said third openings.

16. The process in claim 15 , further comprising a step of sawing said isolating base to isolate said plurality of dies after the step of said welding solder balls.

17. The process in claim 15 , further comprising a step of back lapping said wafer to get a thickness of said wafer around 100-300 μm after the step of said removing said first photo resist pattern.

18. The process in claim 15 , further comprising a step of forming an epoxy layer on back surface of said isolating base.

19. The process in claim 15 , wherein said plurality of dies comprise at least two types of dies.

20. The process in claim 15 , wherein material of said first dielectric layer is SiO 2 by spin coating.

21. The process in claim 15 , wherein material of said isolating base is glass, silicon, ceramic or quartz crystal.

22. The process in claim 15 , wherein material of said material layer is silicon rubber, epoxy, resin, BCB, BT, polyimide (PI) or SINR(Siloxane polymer).

23. The process in claim 15 , wherein material of said second dielectric layer is SINR(Siloxane polymer), BCB or polyimide (PI).

24. The process in claim 15 , further comprising a step of forming a filtering film on said first dielectric layer, said filtering film is an IR filtering layer.

25. The process in claim 15 , wherein material of said contact conductive layer is selected from Ti, Cu and the combination thereof.

26. The process in claim 15 , wherein material of said isolation layer is selected from epoxy, resin and the combination thereof.

27. The process in claim 15 , wherein material of said conductive lines is selected from Ni, Cu, Au and the combination thereof.