Nonvolatile semiconductor device and method of fabricating the same
A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.
1. A stack-type nonvolatile semiconductor device comprising:
a) a first memory device formed on a substrate, the device including:
a semiconductor body elongated in one direction on the substrate, and having a cross section perpendicular to a main surface of the substrate and to the elongated direction, the cross section having a predetermined curvature;
a channel region partially formed on the semiconductor body along the circumference of the semiconductor body;
a tunneling insulating layer disposed on the channel region;
a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region;
a high dielectric constant material layer disposed on the floating gate;
a metallic control gate disposed on the high dielectric constant material layer and electrically insulated from the floating gate; and
source and drain regions which are adjacent to sides of the metallic control gate and formed on the semiconductor body;
an inter-insulating layer disposed on the first memory device; and
a conductive layer disposed on the inter-insulating layer; and
b) a second memory device formed on the conductive layer, the device including:
a semiconductor body elongated in one direction on the conductive layer, and having a cross section perpendicular to a main surface of the conductive layer and to the elongated direction, the cross section having a predetermined curvature;
a channel region partially formed on the semiconductor body along the circumference of the semiconductor body;
a tunneling insulating layer disposed on the channel region;
a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region;
a high dielectric constant material layer disposed on the floating gate;
a metallic control gate disposed on the high dielectric constant material layer and electrically insulated from the floating gate; and
source and drain regions that are adjacent to sides of the metallic control gate and formed on the semiconductor body.
2. The stack-type nonvolatile semiconductor device of claim 1 , further comprising:
a third through N th (N is an integer, and is equal to or greater than 3) memory device that is sequentially stacked on the second memory device, wherein an inter-insulating layer is inserted among the memory devices, the device including:
a semiconductor body elongated in one direction on the conductive layer, and having a cross section perpendicular to a main surface of the conductive layer and to the elongated direction, the cross section having a predetermined curvature;
a channel region partially formed on the semiconductor body along the circumference of the semiconductor body;
a tunneling insulating layer disposed on the channel region;
a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region;
a high dielectric constant material layer disposed on the floating gate;
a metallic control gate disposed on the high dielectric constant material layer and electrically insulated from the floating gate; and
source and drain regions that are adjacent to sides of the metallic control gate and formed on the semiconductor body.
3. The stack-type nonvolatile semiconductor device of claim 1 , wherein the conductive layer is a single-crystalline silicon layer, polycrystalline silicon layer, or a silicon epitaxial layer.
4. The stack-type nonvolatile semiconductor device of claim 1 , wherein the semiconductor body is shaped in a semi-circular, a circular or an oval shape.
5. The stack-type nonvolatile semiconductor device of claim 1 , wherein the substrate is a bulk substrate or a silicon-on-insulator (SOI) substrate.
6. The stack-type nonvolatile semiconductor device of claim 1 , wherein the floating gate is made of a nitride (Si 3 N 4 ) layer.
7. The stack-type nonvolatile semiconductor device of claim 1 , wherein the high dielectric constant material layers are a combination of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 5 ), hafnium silicate (HfSiO), and zirconium silicate (O 4 SiZr).
8. The stack-type nonvolatile semiconductor device of claim 1 , wherein the metallic control gate is made of a metal, metal nitride, metal silicide, or a combination thereof.