IP Library › Granted Patent US 7,515,027
Granted Patent B2
US 7,515,027 · App. 11/353,963 · Granted Apr 7, 2009

Shredded parallel stacked inductor

Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 7,515,027
App. No.
11/353,963
Granted
Apr 7, 2009
Kind
B2
Abstract

A shredded parallel stacked inductor is provided. The shredded parallel stacked inductor includes a substrate, an oxide film formed on the substrate, metallic layers spirally formed within the oxide film, and vias formed in regions of the metallic layers to join the metallic layers in parallel, thus forming a spiral cavity in a center part of the metallic layers.

Claims (13)

1. A shredded parallel stacked inductor comprising:

a substrate;

an oxide film formed on the substrate;

a plurality of metallic layers spirally formed within the oxide film; and

a plurality of vias formed in regions of the plurality of metallic layers to join the plurality of metallic layers in parallel,

wherein a spiral cavity is formed in the plurality of metallic layers.

2. The shredded parallel stacked inductor as claimed in claim 1 , wherein the regions are proximal parts of the plurality of metallic layers.

3. The shredded parallel stacked inductor as claimed in claim 1 , wherein the regions are distal parts of the plurality of metallic layers.

4. The shredded parallel stacked inductor as claimed in claim 1 , wherein the regions are corner parts of the plurality of metallic layers.

5. The shredded parallel stacked inductor as claimed in claim 1 , wherein the spiral cavity is formed in a center part of the plurality of metallic layers except for at the proximal and distal parts of the metallic layers.

6. The shredded parallel stacked inductor as claimed in claim 1 , wherein a current depletion layer of each of the plurality of the metallic layers is reduced by the spiral cavity when electric current is applied to the inductor.

7. The shredded parallel stacked inductor as claimed in claim 1 , wherein the shredded parallel stacked inductor has a structure stacked in parallel by the vias.

8. The shredded parallel stacked inductor as claimed in claim 1 , wherein long sides of the plurality of metallic layers have a length of about 10 μm, and short sides of the plurality of metallic layers have a length of about 3 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2006
From: LEE, JAE-SUP; KIM, SUNG-NAM; LEE, SEONG-SOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 017888/0255 →
Priority Claims (1)
KR 10-2005-0012259 · Feb 15, 2005 · national
Continuity (1)
Related Publication 20060192645A1 · Aug 31, 2006