Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same
An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.
1. An internal reference voltage generating circuit of a semiconductor memory device providing a reference voltage to an input buffer that receives a signal through an input to which an on die termination (ODT) resistor is connected, the circuit comprising:
a voltage dividing circuit arranged in the semiconductor memory device and outputting the reference voltage by dividing a power-supply voltage; and
a pull down driver arranged in the semiconductor memory device and connected to an end of the voltage dividing circuit,
wherein the semiconductor memory device is void of a reference voltage input pin, and
wherein the pull down driver is turned on in a memory write operation according to a write command applied from the outside the semiconductor memory device.
2. The internal reference voltage generating circuit of claim 1 , wherein the voltage dividing circuit comprises: a plurality of resistors serially connected between the power-supply voltage and the pull down driver,
wherein the reference voltage is output from one connection point of the plurality of resistors, and a sum of values of the plurality of resistors is the same as a value of the ODT resistor.
3. The internal reference voltage generating circuit of claim 1 , wherein the voltage dividing circuit comprises:
a first resistor having an end connected to the power-supply voltage and having a value half of a value of the ODT resistor; and
a second resistor having an end connected to the other end of the first resistor and the other end connected to the pull down driver and having a value half of the value of the ODT resistor,
wherein the reference voltage is output from a connection point of the first and second resistors and a sum of values of the first and second resistors is the same as the value of the ODT resistor.
4. The internal reference voltage generating circuit of claim 1 , wherein when the command is a write command the pull down driver is turned on.
5. The internal reference voltage generating circuit of claim 1 , wherein the pull down driver has a same on resistor value as an on resistor value of a pull down driver of an output driver of a memory controller that transmits data to the input of the semiconductor memory device.
6. A semiconductor memory device comprising:
an input receiving a data signal;
an on die termination (ODT) resistor connected to the input;
an input buffer that receives the data signal through the input based on a reference voltage fed thereto; and
an internal reference voltage generating circuit that generates the reference voltage,
wherein the internal reference voltage generating circuit includes:
a voltage dividing circuit outputting the reference voltage by dividing a power-supply voltage;
a pull down driver connected to an end of the voltage dividing circuit,
wherein the semiconductor memory device is void of a reference voltage input, and
wherein the pull down driver is turned on in a memory write operation according to a write command applied from the outside the semiconductor memory device.
7. The semiconductor memory device of claim 6 , wherein the voltage dividing circuit comprises: a plurality of resistors serially connected between the power-supply voltage and the pull down driver,
wherein the reference voltage is output from one connection point of the plurality of resistors, and a sum of values of the plurality of resistors is the same as a value of the ODT resistor.
8. The semiconductor memory device of claim 6 , wherein the voltage dividing circuit comprises:
a first resistor having an end connected to the power-supply voltage, and having a value half of a value of the ODT resistor; and
a second resistor having an end connected to the other end of the first resistor and the other end connected to the pull down driver, and having a value half of the value of the ODT resistor,
wherein the reference voltage is output from a connection point of the first and second resistors and a sum of the values of the first and second resistors is the same as the value of the ODT resistor.
9. The semiconductor memory device of claim 6 , wherein when the command is a write command the pull down driver is turned on.
10. The semiconductor memory device of claim 6 , wherein the pull down driver has a same on resistor value as an on resistor value of a pull down driver of an output driver of a memory controller that transmits data to the input.