Wide-input windowed nonlinear analog-to-digital converter for high-frequency digitally controlled SMPS
In embodiments, a new analog-to-digital converter (ADC) architecture can be used with switch-mode power supplies (SMPS) operating at switching frequencies higher than 10 MHz. Analog-to-digital converter embodiments can achieve very low power consumption, fast conversion time, and can be implemented with a simple hardware. Another noteworthy benefit is that certain ADC embodiments feature a non-linear gain characteristic that provides improved load transient response for digital controllers.
1. An Analog-to-Digital Converter (ADC) circuit comprising:
a first differential input stage and a second differential input state to receive input voltages as low as zero volts and to produce a reference bias voltage and an output bias voltage;
a reference delay line to receive the reference bias voltage and an output measurement delay line to receive the output bias voltage, each containing different numbers of delay cells; and
an error decoder to determine an output voltage error by comparing propagation times of a clock signal (CLK) through the reference delay line and the output measurement delay line and send a digital equivalent of the output voltage error to a digital compensator.
2. The circuit of claim 1 , wherein the reference delay line and the output measurement delay line are triggered simultaneously, with the rising edge of CLK signal initiating movement of two pulses through them.
3. The circuit of claim 1 , wherein a strobe signal is created and a snapshot of the measured delay line is taken when a pulse propagating through the reference delay line reaches an N th delay cell.
4. The circuit of claim 3 , wherein the error decoder determines e[n], a digital equivalent of output voltage error, based on the number of cells the clock (CLK) signal has propagated through.
5. The circuit of claim 1 , wherein the delay cells in at least one of the reference delay line and the output measurement delay line are digitally programmable to vary conversion time.
6. The circuit of claim 1 , wherein the delay cells in at least one of the reference delay line and the output measurement delay line are digitally programmable to dynamically vary quantization steps.
7. The circuit of claim 1 , wherein the ADC is powered down after conversion to reduce power consumption.
8. The circuit of claim 1 , wherein the digital compensator is coupled with a digital pulse width modulator to control a switch-mode power supplies (SMPS).
9. The circuit of claim 1 , wherein difference in propagation of a clock signal through the reference delay line and the output measurement delay line is substantially independent of changes to the input voltage, V ref .
10. The circuit of claim 1 , wherein a zero error b in is larger than other quantization steps when there is a significant difference between V ref and converter output voltage to provide a non-linear gain characteristic.