Sense amplifier of semiconductor memory device
A sense amplifier of a semiconductor device is disclosed. The sense amplifier includes first and second PMOS transistors connected to each other at sources of the first and second PMOS transistors, and first and second NMOS transistors connected to each other at sources of the first and second NMOS transistors, to detect and amplify a voltage difference between a specific bit line and a complementary bit line. The second NMOS transistor and second PMOS transistor are connected to the specific bit line via a column select switch at drains of the second NMOS transistor and second PMOS transistor. The first PMOS transistor and first NMOS transistor are connected to the specific bit line via the column select switch at gates of the first PMOS transistor and first NMOS transistor. The second NMOS transistor, the second PMOS transistor, the first PMOS transistor, and the first NMOS transistor are arranged, in this order, downstream from the column select switch.
1. A sense amplifier of a semiconductor device comprising first and second PMOS transistors connected to each other at sources of the first and second PMOS transistors, and first and second NMOS transistors connected to each other at sources of the first and second NMOS transistors, to detect and amplify a voltage difference between a specific bit line and a complementary bit line, wherein:
the second NMOS transistor and second PMOS transistor are connected to the specific bit line via a column select switch at drains of the second NMOS transistor and second PMOS transistor, and the first PMOS transistor and first NMOS transistor are connected to the specific bit line via the column select switch at gates of the first PMOS transistor and first NMOS transistor; and
the second NMOS transistor, the second PMOS transistor, the first PMOS transistor, and the first NMOS transistor are arranged, in this order, downstream from the column select switch.
2. The sense amplifier according to claim 1 , wherein, when a read command is activated, the column select switch connects the specific bit line to a local input/output line, and the specific bit line is increased in potential due to a charge sharing between the specific bit line and the local input/output line.
3. The sense amplifier according to claim 1 , wherein the specific bit line has a first potential lower than a second potential of the local input/output line, and when charge is input to the specific bit line, upon an activation of a read command, the second NMOS transistor sinks the charge through a channel of the second NMOS transistor.
4. The sense amplifier according to claim 1 , wherein a bit line equalizer circuit is arranged between the column select switch and the second NMOS transistor.
5. A sense amplifier of a semiconductor device comprising first and second PMOS transistors connected to each other at sources of the first and second PMOS transistors, and first and second NMOS transistors connected to each other at sources of the first and second NMOS transistors, to detect and amplify a voltage difference between a specific bit line and a complementary bit line, wherein:
the first NMOS transistor is connected to the specific bit line at a gate of the first NMOS transistor, and the second NMOS transistor is connected to the specific bit line at a drain of the second NMOS transistor; and
the first and second NMOS transistors are arranged such that the first NMOS transistor is physically spaced apart from a column select switch by a first distance greater than a second distance between the second NMOS transistor and the column select switch.
6. The sense amplifier according to claim 5 , wherein, when a read command is activated, the column select switch connects the specific bit line to the local input/output line, and the specific bit line is increased in potential due to a charge sharing between the specific bit line and the local input/output line.
7. The sense amplifier according to claim 5 , wherein the specific bit line has a potential lower than a potential of the local input/output line and when charge is input to the bit line, upon an activation of a read command, the second NMOS transistor sinks the charge through a channel of the second NMOS transistor.
8. The sense amplifier according to claim 5 , wherein a bit line equalizer circuit is arranged between the column select switch and the second NMOS transistor.