Self-aligned split gate memory cell and method of forming
A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.
1. A method of forming a split gate memory device in and on a semiconductor layer, comprising:
forming an insulating layer over the semiconductor layer;
patterning the insulating layer to leave a pillar of insulating material, wherein the pillar has a first side and a second side;
forming a gate dielectric over the semiconductor layer;
forming a charge storage layer over the gate dielectric and along the first and second sides of and over the pillar;
after forming the charge storage layer, forming a gate material layer over the gate dielectric and the pillar;
performing an etch to leave a first portion of the gate material layer laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material layer laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate; and
forming source/drain regions in the semiconductor layer spaced apart to form a channel under the first and second portions of the gate material layer.
2. The method of claim 1 , wherein the step of forming the insulating layer comprises performing a first step of thermal oxidation.
3. The method of claim 2 , wherein the step of forming the gate dielectric comprises performing a second step of thermal oxidation.
4. The method of claim 1 , wherein the step of forming the gate material layer comprises depositing polysilicon.
5. The method of claim 1 , wherein the step of forming the charge storage layer comprises:
forming nanocrystals; and
surrounding the nanocrystals with a layer of oxide.
6. The method of claim 1 , wherein the step of forming the charge storage layer comprises depositing nitride.
7. The method of claim 1 , wherein the step of patterning the insulating layer, comprises:
depositing a sacrificial layer,
patterning the sacrificial layer to form a sacrificial pillar of a first width; and
thinning the sacrificial layer to reduce the sacrificial pillar to a second width less than the first width.
8. The method of claim 7 , wherein the step of patterning the sacrificial layer, further comprises:
depositing a layer of photoresist on the sacrificial layer;
patterning the layer of photoresist to form a pillar of photoresist of a third width; and
thinning the pillar of photoresist to reduce the pillar of photoresist to a fourth width less than the third width.
9. The method of claim 7 , wherein the step of patterning the insulating layer is further characterized by the sacrificial layer comprising polysilicon.
10. The method of claim 1 , wherein the step of forming source/drain regions comprises performing an implant using the first and second portions of the gate material layer as a mask.
11. The method of claim 10 , wherein the step of forming source/drain regions further comprises:
forming a sidewall spacer adjacent to the first and second portions of the gate material layer; and
performing a second implant using the sidewall spacer as a mask.
12. A method of forming a split gate memory device in and on a semiconductor layer, comprising:
forming a pillar of insulating material over the semiconductor layer having a first side and a second side;
forming a charge storage layer over and along the first and second sides of the pillar and over the semiconductor layer;
depositing a substantially conformal layer of gate material over the charge storage layer;
performing an anisotropic etch on the substantially conformal layer so that first sidewall spacers of the gate material are formed adjacent to the first and second sides of the pillar of insulating material;
performing a first implant into the semiconductor layer using the first sidewall spacers as a mask;
forming second sidewall spacers adjacent to the first sidewall spacers; and
performing a second implant into the semiconductor layer using the second sidewall spacers as a mask.
13. The method of claim 12 , wherein the step of forming the pillar comprises:
performing a step of thermal oxidation on the semiconductor layer to form an insulating layer;
depositing a sacrificial layer;
patterning the sacrificial layer to form a patterned portion of the sacrificial layer; and
etching the insulating layer using the patterned portion as a mask.
14. The method of claim 13 , wherein the step of patterning the sacrificial layer comprises:
forming a layer of photoresist over the sacrificial layer;
forming a pillar of photoresist;
thinning the pillar of photoresist,
applying an etchant to the sacrificial layer after the step of thinning the pillar of photoresist;
removing the pillar of photoresist; and
after the step of applying the etchant, performing thinning to form the patterned portion of the sacrificial layer.
15. The method of claim 14 , wherein the depositing the sacrificial layer comprises depositing polyslicon.
16. The method of claim 12 , further comprising performing a step of thermal oxidation on the semiconductor layer prior to the step of forming the charge storage layer.