Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
1. A semiconductor structure containing a vertical transistor, comprising:
a substrate, wherein at least a portion of the work surface of the substrate is formed of polysilicon;
a polysilicon pillar extending vertically from the polysilicon surface of the substrate, the pillar having a top end, a top portion, a central portion, and a bottom portion;
a first source/drain region defined in the top portion of the pillar;
a channel region defined in the central portion of the pillar;
a second source/drain region defined in the bottom portion of the pillar;
a dielectric layer surrounding the central portion of the pillar and being in alignment with the channel region of the transistor;
a transistor gate surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor; and
a spacer layer formed around only the top portion of the pillar and the first source/drain region.
2. The structure according to claim 1 , wherein the thickness of the transistor gate corresponds with the thickness of the spacer layer.
3. The structure according to claim 2 , wherein the top end of the pillar has been silicided.
4. The structure according to claim 2 , wherein the spacer layer comprises a nitride material.
5. The structure according to claim 1 , further comprising a conductive path extending away from the transistor gate, wherein the conductive path and the transistor gate are formed of the same material, and the conductive path is formed as an extension of the transistor gate.
6. The structure according to claim 5 , wherein the transistor gate and conductive path are formed of metal.
7. The structure according to claim 5 , wherein the transistor gate and conductive path are formed of polysilicon.
8. The structure according to claim 7 , wherein the conductive path in a silicided conductive path.
9. The structure according to claim 5 , further comprising at least one conductive plug, each conductive plug respectively contacting one of the first source/drain region, the polysilicon portion of the substrate from which the pillar extends, and the conductive path extending from the transistor gate.